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kdcom.h
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1/*++
2
3Copyright (c) Microsoft Corporation. All rights reserved.
4
5Module Name:
6
7 kdcom.h
8
9Abstract:
10
11 Contains constants used when interacting with 16550-based serial ports.
12
13Author:
14
15 Bryan M. Willman (bryanwi) 24-Sep-1990
16
17Revision History:
18
19 John Vert (jvert) 19-Jul-1991
20 Moved into HAL
21
22--*/
23
24#pragma once
25
26#define COM1_PORT 0x03F8
27#define COM2_PORT 0x02F8
28#define COM3_PORT 0x03E8
29#define COM4_PORT 0x02E8
30
31#define COM_DAT 0x00
32#define COM_IEN 0x01 // interrupt enable register
33#define COM_FCR 0x02 // fifo control register
34#define COM_LCR 0x03 // line control register
35#define COM_MCR 0x04 // modem control register
36#define COM_LSR 0x05 // line status register
37#define COM_MSR 0x06 // modem status register
38#define COM_SCR 0x07 // scratch register
39#define COM_DLL 0x00 // divisor latch least sig
40#define COM_DLM 0x01 // divisor latch most sig
41
42#define COM_BI 0x10 // Break detect
43#define COM_FE 0x08 // Framing error
44#define COM_PE 0x04 // Parity error
45#define COM_OE 0x02 // Overrun error
46
47#define LC_DLAB 0x80 // LCR divisor latch access bit
48
49#define CLOCK_RATE 115200 // Hardware base clock frequency
50
51#define MC_DTRRTS 0x03 // Control bits to assert DTR and RTS
52#define MS_DSRCTSCD 0xB0 // Status bits for DSR, CTS and CD
53#define MS_CD 0x80 // MSR bit to indicate carrier detect
54
55#define FC_ENABLE 0x01 // FCR control bit to enable the FIFO
56#define FC_CLEAR_RECEIVE 0x02 // FCR control bit to clear receive FIFO
57#define FC_CLEAR_TRANSMIT 0x04 // FCR control bit to clear transmit FIFO
58
59#define COM_OUTRDY 0x20 // LSR bit to indicate transmitter is empty
60#define COM_DATRDY 0x01 // LSR bit to indicate data is available
61
62#define BD_150 150
63#define BD_300 300
64#define BD_600 600
65#define BD_1200 1200
66#define BD_2400 2400
67#define BD_4800 4800
68#define BD_9600 9600
69#define BD_14400 14400
70#define BD_19200 19200
71#define BD_56000 56000
72#define BD_57600 57600
73#define BD_115200 115200
74
75//
76// This bit controls the loopback testing mode of the device. Basically
77// the outputs are connected to the inputs (and vice versa).
78//
79
80#define SERIAL_MCR_LOOP 0x10
81
82//
83// This bit is used for general purpose output.
84//
85
86#define SERIAL_MCR_OUT1 0x04
87
88//
89// This bit contains the (complemented) state of the clear to send
90// (CTS) line.
91//
92
93#define SERIAL_MSR_CTS 0x10
94
95//
96// This bit contains the (complemented) state of the data set ready
97// (DSR) line.
98//
99
100#define SERIAL_MSR_DSR 0x20
101
102//
103// This bit contains the (complemented) state of the ring indicator
104// (RI) line.
105//
106
107#define SERIAL_MSR_RI 0x40
108
109//
110// This bit contains the (complemented) state of the data carrier detect
111// (DCD) line.
112//
113
114#define SERIAL_MSR_DCD 0x80
115
116#define SERIAL_LSR_NOT_PRESENT 0xff