Apic.h File Reference

Headers relating to Advanced Programmable Interrupt Controller (APIC). More...

Go to the source code of this file.

Classes
struct	_IO_APIC_ENT

Macros
#define	X2_MSR_BASE   0x800
#define	ICROffset   0x300
#define	TO_X2(x)
#define	APIC_DEFAULT_PHYS_BASE   0xfee00000
#define	APIC_BSP   (1UL << 8)
#define	APIC_EXTD   (1UL << 10)
#define	APIC_EN   (1UL << 11)
#define	APIC_LVR   0x30
#define	APIC_LVR_MASK   0xFF00FF
#define	GET_APIC_VERSION(x)
#define	GET_APIC_MAXLVT(x)
#define	APIC_INTEGRATED(x)
#define	APIC_XAPIC(x)
#define	APIC_TASKPRI   0x80
#define	APIC_TPRI_MASK   0xFFu
#define	APIC_ARBPRI   0x90
#define	APIC_ARBPRI_MASK   0xFFu
#define	APIC_PROCPRI   0xA0
#define	APIC_EIO_ACK   0x0
#define	APIC_RRR   0xC0
#define	APIC_LDR   0xD0
#define	APIC_LDR_MASK   (0xFFu << 24)
#define	GET_APIC_LOGICAL_ID(x)
#define	SET_APIC_LOGICAL_ID(x)
#define	APIC_ALL_CPUS   0xFFu
#define	APIC_DFR   0xE0
#define	APIC_DFR_CLUSTER   0x0FFFFFFFul
#define	APIC_DFR_FLAT   0xFFFFFFFFul
#define	APIC_SPIV   0xF0
#define	APIC_SPIV_FOCUS_DISABLED   (1 << 9)
#define	APIC_SPIV_APIC_ENABLED   (1 << 8)
#define	APIC_ISR   0x100
#define	APIC_ISR_NR   0x8 /* Number of 32 bit ISR registers. */
#define	APIC_TMR   0x180
#define	APIC_IRR   0x200
#define	APIC_ESR   0x280
#define	APIC_ESR_SEND_CS   0x00001
#define	APIC_ESR_RECV_CS   0x00002
#define	APIC_ESR_SEND_ACC   0x00004
#define	APIC_ESR_RECV_ACC   0x00008
#define	APIC_ESR_SENDILL   0x00020
#define	APIC_ESR_RECVILL   0x00040
#define	APIC_ESR_ILLREGA   0x00080
#define	APIC_CMCI   0x2F0
#define	APIC_ICR   0x300
#define	APIC_DEST_SELF   0x40000
#define	APIC_DEST_ALLINC   0x80000
#define	APIC_DEST_ALLBUT   0xC0000
#define	APIC_ICR_RR_MASK   0x30000
#define	APIC_ICR_RR_INVALID   0x00000
#define	APIC_ICR_RR_INPROG   0x10000
#define	APIC_ICR_RR_VALID   0x20000
#define	APIC_INT_LEVELTRIG   0x08000
#define	APIC_INT_ASSERT   0x04000
#define	APIC_ICR_BUSY   0x01000
#define	APIC_DEST_LOGICAL   0x00800
#define	APIC_DEST_PHYSICAL   0x00000
#define	APIC_DM_FIXED   0x00000
#define	APIC_DM_LOWEST   0x00100
#define	APIC_DM_SMI   0x00200
#define	APIC_DM_REMRD   0x00300
#define	APIC_DM_NMI   0x00400
#define	APIC_DM_INIT   0x00500
#define	APIC_DM_STARTUP   0x00600
#define	APIC_DM_EXTINT   0x00700
#define	APIC_VECTOR_MASK   0x000FF
#define	APIC_ICR2   0x310
#define	GET_APIC_DEST_FIELD(x)
#define	SET_APIC_DEST_FIELD(x)
#define	APIC_LVTT   0x320
#define	APIC_LVTTHMR   0x330
#define	APIC_LVTPC   0x340
#define	APIC_LVT0   0x350
#define	APIC_LVT_TIMER_BASE_MASK   (0x3 << 18)
#define	GET_APIC_TIMER_BASE(x)
#define	SET_APIC_TIMER_BASE(x)
#define	APIC_TIMER_BASE_CLKIN   0x0
#define	APIC_TIMER_BASE_TMBASE   0x1
#define	APIC_TIMER_BASE_DIV   0x2
#define	APIC_LVT_TIMER_MASK   (3 << 17)
#define	APIC_LVT_TIMER_ONESHOT   (0 << 17)
#define	APIC_LVT_TIMER_PERIODIC   (1 << 17)
#define	APIC_LVT_TIMER_TSCDEADLINE   (2 << 17)
#define	APIC_LVT_MASKED   (1 << 16)
#define	APIC_LVT_LEVEL_TRIGGER   (1 << 15)
#define	APIC_LVT_REMOTE_IRR   (1 << 14)
#define	APIC_INPUT_POLARITY   (1 << 13)
#define	APIC_SEND_PENDING   (1 << 12)
#define	APIC_MODE_MASK   0x700
#define	GET_APIC_DELIVERY_MODE(x)
#define	SET_APIC_DELIVERY_MODE(x, y)
#define	APIC_MODE_FIXED   0x0
#define	APIC_MODE_NMI   0x4
#define	APIC_MODE_EXTINT   0x7
#define	APIC_LVT1   0x360
#define	APIC_LVTERR   0x370
#define	APIC_TMICT   0x380
#define	APIC_TMCCT   0x390
#define	APIC_TDCR   0x3E0
#define	APIC_SELF_IPI   0x3F0
#define	APIC_TDR_DIV_TMBASE   (1 << 2)
#define	APIC_TDR_DIV_1   0xB
#define	APIC_TDR_DIV_2   0x0
#define	APIC_TDR_DIV_4   0x1
#define	APIC_TDR_DIV_8   0x2
#define	APIC_TDR_DIV_16   0x3
#define	APIC_TDR_DIV_32   0x8
#define	APIC_TDR_DIV_64   0x9
#define	APIC_TDR_DIV_128   0xA
#define	APIC_EILVT0   0x500
#define	APIC_EILVT_NR_AMD_K8   1 /* # of extended interrupts */
#define	APIC_EILVT_NR_AMD_10H   4
#define	APIC_EILVT_LVTOFF(x)
#define	APIC_EILVT_MSG_FIX   0x0
#define	APIC_EILVT_MSG_SMI   0x2
#define	APIC_EILVT_MSG_NMI   0x4
#define	APIC_EILVT_MSG_EXT   0x7
#define	APIC_EILVT_MASKED   (1 << 16)
#define	APIC_EILVT1   0x510
#define	APIC_EILVT2   0x520
#define	APIC_EILVT3   0x530
#define	APIC_BASE_MSR   0x800
#define	APIC_BASE_MSR   0x800
#define	IO_APIC_DEFAULT_BASE_ADDR   0xFEC00000
#define	IOAPIC_APPEND_QWORD(hi, lo)
#define	IOAPIC_LOW_DWORD(x)
#define	IOAPIC_HIGH_DWORD(x)
#define	IOAPIC_REDTBL(x)
#define	IOAPIC_REDTBL_MAX   (24)
#define	LU_SIZE   0x400
#define	LU_ID_REGISTER   0x00000020
#define	LU_VERS_REGISTER   0x00000030
#define	LU_TPR   0x00000080
#define	LU_APR   0x00000090
#define	LU_PPR   0x000000A0
#define	LU_EOI   0x000000B0
#define	LU_REMOTE_REGISTER   0x000000C0
#define	LU_DEST   0x000000D0
#define	LU_DEST_FORMAT   0x000000E0
#define	LU_SPURIOUS_VECTOR   0x000000F0
#define	LU_FAULT_VECTOR   0x00000370
#define	LU_ISR_0   0x00000100
#define	LU_TMR_0   0x00000180
#define	LU_IRR_0   0x00000200
#define	LU_ERROR_STATUS   0x00000280
#define	LU_INT_CMD_LOW   0x00000300
#define	LU_INT_CMD_HIGH   0x00000310
#define	LU_TIMER_VECTOR   0x00000320
#define	LU_INT_VECTOR_0   0x00000350
#define	LU_INT_VECTOR_1   0x00000360
#define	LU_INITIAL_COUNT   0x00000380
#define	LU_CURRENT_COUNT   0x00000390
#define	LU_DIVIDER_CONFIG   0x000003E0
#define	IO_REGISTER_SELECT   0x00000000
#define	IO_REGISTER_WINDOW   0x00000010
#define	IO_ID_REGISTER   0x00000000
#define	IO_VERS_REGISTER   0x00000001
#define	IO_ARB_ID_REGISTER   0x00000002
#define	IO_REDIR_BASE   0x00000010

Typedefs
typedef struct _IO_APIC_ENT	IO_APIC_ENT
typedef struct _IO_APIC_ENT *	PIO_APIC_ENT

Functions
BOOLEAN	ApicInitialize ()
	Initialize APIC.
VOID	ApicUninitialize ()
	Uninitialize APIC.
BOOLEAN	ApicStoreLocalApicFields (PLAPIC_PAGE LApicBuffer, PBOOLEAN IsUsingX2APIC)
	Store the details of APIC in xAPIC and x2APIC mode.
BOOLEAN	ApicStoreIoApicFields (IO_APIC_ENTRY_PACKETS *IoApicPackets)
	Store the details of I/O APIC.
VOID	ApicSelfIpi (UINT32 Vector)
	Self IPI the current core.
VOID	ApicTriggerGenericNmi ()
	Trigger NMI on X2APIC or APIC based on Current system.

Detailed Description

Headers relating to Advanced Programmable Interrupt Controller (APIC).

Author

Sina Karvandi (sina@.nosp@m.hype.nosp@m.rdbg..nosp@m.org)

Some of the constants are copied from KVM project

Version

0.1

Date

2020-12-31

Copyright

This project is released under the GNU Public License v3.

Macro Definition Documentation

APIC_ALL_CPUS

#define APIC_ALL_CPUS   0xFFu

APIC_ARBPRI

#define APIC_ARBPRI   0x90

APIC_ARBPRI_MASK

#define APIC_ARBPRI_MASK   0xFFu

APIC_BASE_MSR [1/2]

#define APIC_BASE_MSR   0x800

APIC_BASE_MSR [2/2]

#define APIC_BASE_MSR   0x800

APIC_BSP

#define APIC_BSP   (1UL << 8)

APIC_CMCI

#define APIC_CMCI   0x2F0

APIC_DEFAULT_PHYS_BASE

#define APIC_DEFAULT_PHYS_BASE   0xfee00000

APIC_DEST_ALLBUT

#define APIC_DEST_ALLBUT   0xC0000

APIC_DEST_ALLINC

#define APIC_DEST_ALLINC   0x80000

APIC_DEST_LOGICAL

#define APIC_DEST_LOGICAL   0x00800

APIC_DEST_PHYSICAL

#define APIC_DEST_PHYSICAL   0x00000

APIC_DEST_SELF

#define APIC_DEST_SELF   0x40000

APIC_DFR

#define APIC_DFR   0xE0

APIC_DFR_CLUSTER

#define APIC_DFR_CLUSTER   0x0FFFFFFFul

APIC_DFR_FLAT

#define APIC_DFR_FLAT   0xFFFFFFFFul

APIC_DM_EXTINT

#define APIC_DM_EXTINT   0x00700

APIC_DM_FIXED

#define APIC_DM_FIXED   0x00000

APIC_DM_INIT

#define APIC_DM_INIT   0x00500

APIC_DM_LOWEST

#define APIC_DM_LOWEST   0x00100

APIC_DM_NMI

#define APIC_DM_NMI   0x00400

APIC_DM_REMRD

#define APIC_DM_REMRD   0x00300

APIC_DM_SMI

#define APIC_DM_SMI   0x00200

APIC_DM_STARTUP

#define APIC_DM_STARTUP   0x00600

APIC_EILVT0

#define APIC_EILVT0   0x500

APIC_EILVT1

#define APIC_EILVT1   0x510

APIC_EILVT2

#define APIC_EILVT2   0x520

APIC_EILVT3

#define APIC_EILVT3   0x530

APIC_EILVT_LVTOFF

#define APIC_EILVT_LVTOFF

(

x

)

Value:

(((x) >> 4) & 0xF)

APIC_EILVT_MASKED

#define APIC_EILVT_MASKED   (1 << 16)

APIC_EILVT_MSG_EXT

#define APIC_EILVT_MSG_EXT   0x7

APIC_EILVT_MSG_FIX

#define APIC_EILVT_MSG_FIX   0x0

APIC_EILVT_MSG_NMI

#define APIC_EILVT_MSG_NMI   0x4

APIC_EILVT_MSG_SMI

#define APIC_EILVT_MSG_SMI   0x2

APIC_EILVT_NR_AMD_10H

#define APIC_EILVT_NR_AMD_10H   4

APIC_EILVT_NR_AMD_K8

#define APIC_EILVT_NR_AMD_K8   1 /* # of extended interrupts */

APIC_EIO_ACK

#define APIC_EIO_ACK   0x0

APIC_EN

#define APIC_EN   (1UL << 11)

APIC_ESR

#define APIC_ESR   0x280

APIC_ESR_ILLREGA

#define APIC_ESR_ILLREGA   0x00080

APIC_ESR_RECV_ACC

#define APIC_ESR_RECV_ACC   0x00008

APIC_ESR_RECV_CS

#define APIC_ESR_RECV_CS   0x00002

APIC_ESR_RECVILL

#define APIC_ESR_RECVILL   0x00040

APIC_ESR_SEND_ACC

#define APIC_ESR_SEND_ACC   0x00004

APIC_ESR_SEND_CS

#define APIC_ESR_SEND_CS   0x00001

APIC_ESR_SENDILL

#define APIC_ESR_SENDILL   0x00020

APIC_EXTD

#define APIC_EXTD   (1UL << 10)

APIC_ICR

#define APIC_ICR   0x300

APIC_ICR2

#define APIC_ICR2   0x310

APIC_ICR_BUSY

#define APIC_ICR_BUSY   0x01000

APIC_ICR_RR_INPROG

#define APIC_ICR_RR_INPROG   0x10000

APIC_ICR_RR_INVALID

#define APIC_ICR_RR_INVALID   0x00000

APIC_ICR_RR_MASK

#define APIC_ICR_RR_MASK   0x30000

APIC_ICR_RR_VALID

#define APIC_ICR_RR_VALID   0x20000

APIC_INPUT_POLARITY

#define APIC_INPUT_POLARITY   (1 << 13)

APIC_INT_ASSERT

#define APIC_INT_ASSERT   0x04000

APIC_INT_LEVELTRIG

#define APIC_INT_LEVELTRIG   0x08000

APIC_INTEGRATED

#define APIC_INTEGRATED

(

x

)

Value:

(1)

APIC_IRR

#define APIC_IRR   0x200

APIC_ISR

#define APIC_ISR   0x100

APIC_ISR_NR

#define APIC_ISR_NR   0x8 /* Number of 32 bit ISR registers. */

APIC_LDR

#define APIC_LDR   0xD0

APIC_LDR_MASK

#define APIC_LDR_MASK   (0xFFu << 24)

APIC_LVR

#define APIC_LVR   0x30

APIC_LVR_MASK

#define APIC_LVR_MASK   0xFF00FF

APIC_LVT0

#define APIC_LVT0   0x350

APIC_LVT1

#define APIC_LVT1   0x360

APIC_LVT_LEVEL_TRIGGER

#define APIC_LVT_LEVEL_TRIGGER   (1 << 15)

APIC_LVT_MASKED

#define APIC_LVT_MASKED   (1 << 16)

APIC_LVT_REMOTE_IRR

#define APIC_LVT_REMOTE_IRR   (1 << 14)

APIC_LVT_TIMER_BASE_MASK

#define APIC_LVT_TIMER_BASE_MASK   (0x3 << 18)

APIC_LVT_TIMER_MASK

#define APIC_LVT_TIMER_MASK   (3 << 17)

APIC_LVT_TIMER_ONESHOT

#define APIC_LVT_TIMER_ONESHOT   (0 << 17)

APIC_LVT_TIMER_PERIODIC

#define APIC_LVT_TIMER_PERIODIC   (1 << 17)

APIC_LVT_TIMER_TSCDEADLINE

#define APIC_LVT_TIMER_TSCDEADLINE   (2 << 17)

APIC_LVTERR

#define APIC_LVTERR   0x370

APIC_LVTPC

#define APIC_LVTPC   0x340

APIC_LVTT

#define APIC_LVTT   0x320

APIC_LVTTHMR

#define APIC_LVTTHMR   0x330

APIC_MODE_EXTINT

#define APIC_MODE_EXTINT   0x7

APIC_MODE_FIXED

#define APIC_MODE_FIXED   0x0

APIC_MODE_MASK

#define APIC_MODE_MASK   0x700

APIC_MODE_NMI

#define APIC_MODE_NMI   0x4

APIC_PROCPRI

#define APIC_PROCPRI   0xA0

APIC_RRR

#define APIC_RRR   0xC0

APIC_SELF_IPI

#define APIC_SELF_IPI   0x3F0

APIC_SEND_PENDING

#define APIC_SEND_PENDING   (1 << 12)

APIC_SPIV

#define APIC_SPIV   0xF0

APIC_SPIV_APIC_ENABLED

#define APIC_SPIV_APIC_ENABLED   (1 << 8)

APIC_SPIV_FOCUS_DISABLED

#define APIC_SPIV_FOCUS_DISABLED   (1 << 9)

APIC_TASKPRI

#define APIC_TASKPRI   0x80

APIC_TDCR

#define APIC_TDCR   0x3E0

APIC_TDR_DIV_1

#define APIC_TDR_DIV_1   0xB

APIC_TDR_DIV_128

#define APIC_TDR_DIV_128   0xA

APIC_TDR_DIV_16

#define APIC_TDR_DIV_16   0x3

APIC_TDR_DIV_2

#define APIC_TDR_DIV_2   0x0

APIC_TDR_DIV_32

#define APIC_TDR_DIV_32   0x8

APIC_TDR_DIV_4

#define APIC_TDR_DIV_4   0x1

APIC_TDR_DIV_64

#define APIC_TDR_DIV_64   0x9

APIC_TDR_DIV_8

#define APIC_TDR_DIV_8   0x2

APIC_TDR_DIV_TMBASE

#define APIC_TDR_DIV_TMBASE   (1 << 2)

APIC_TIMER_BASE_CLKIN

#define APIC_TIMER_BASE_CLKIN   0x0

APIC_TIMER_BASE_DIV

#define APIC_TIMER_BASE_DIV   0x2

APIC_TIMER_BASE_TMBASE

#define APIC_TIMER_BASE_TMBASE   0x1

APIC_TMCCT

#define APIC_TMCCT   0x390

APIC_TMICT

#define APIC_TMICT   0x380

APIC_TMR

#define APIC_TMR   0x180

APIC_TPRI_MASK

#define APIC_TPRI_MASK   0xFFu

APIC_VECTOR_MASK

#define APIC_VECTOR_MASK   0x000FF

APIC_XAPIC

#define APIC_XAPIC

(

x

)

Value:

((x) >= 0x14)

GET_APIC_DELIVERY_MODE

#define GET_APIC_DELIVERY_MODE

(

x

)

Value:

(((x) >> 8) & 0x7)

GET_APIC_DEST_FIELD

#define GET_APIC_DEST_FIELD

(

x

)

Value:

(((x) >> 24) & 0xFF)

GET_APIC_LOGICAL_ID

#define GET_APIC_LOGICAL_ID

(

x

)

Value:

(((x) >> 24) & 0xFFu)

GET_APIC_MAXLVT

#define GET_APIC_MAXLVT

(

x

)

Value:

(((x) >> 16) & 0xFFu)

GET_APIC_TIMER_BASE

#define GET_APIC_TIMER_BASE

(

x

)

Value:

(((x) >> 18) & 0x3)

GET_APIC_VERSION

#define GET_APIC_VERSION

(

x

)

Value:

((x) & 0xFFu)

ICROffset

#define ICROffset   0x300

IO_APIC_DEFAULT_BASE_ADDR

#define IO_APIC_DEFAULT_BASE_ADDR   0xFEC00000

IO_ARB_ID_REGISTER

#define IO_ARB_ID_REGISTER   0x00000002

IO_ID_REGISTER

#define IO_ID_REGISTER   0x00000000

IO_REDIR_BASE

#define IO_REDIR_BASE   0x00000010

IO_REGISTER_SELECT

#define IO_REGISTER_SELECT   0x00000000

IO_REGISTER_WINDOW

#define IO_REGISTER_WINDOW   0x00000010

IO_VERS_REGISTER

#define IO_VERS_REGISTER   0x00000001

IOAPIC_APPEND_QWORD

#define IOAPIC_APPEND_QWORD	(		hi,
			lo )

Value:

(((UINT64)(hi) << 32) | (UINT64)(lo))

IOAPIC_HIGH_DWORD

#define IOAPIC_HIGH_DWORD

(

x

)

Value:

((UINT32)((x) >> 32))

IOAPIC_LOW_DWORD

#define IOAPIC_LOW_DWORD

(

x

)

Value:

((UINT32)(x))

IOAPIC_REDTBL

#define IOAPIC_REDTBL

(

x

)

Value:

(0x10 + (x) * 2)

IOAPIC_REDTBL_MAX

#define IOAPIC_REDTBL_MAX   (24)

LU_APR

#define LU_APR   0x00000090

LU_CURRENT_COUNT

#define LU_CURRENT_COUNT   0x00000390

LU_DEST

#define LU_DEST   0x000000D0

LU_DEST_FORMAT

#define LU_DEST_FORMAT   0x000000E0

LU_DIVIDER_CONFIG

#define LU_DIVIDER_CONFIG   0x000003E0

LU_EOI

#define LU_EOI   0x000000B0

LU_ERROR_STATUS

#define LU_ERROR_STATUS   0x00000280

LU_FAULT_VECTOR

#define LU_FAULT_VECTOR   0x00000370

LU_ID_REGISTER

#define LU_ID_REGISTER   0x00000020

LU_INITIAL_COUNT

#define LU_INITIAL_COUNT   0x00000380

LU_INT_CMD_HIGH

#define LU_INT_CMD_HIGH   0x00000310

LU_INT_CMD_LOW

#define LU_INT_CMD_LOW   0x00000300

LU_INT_VECTOR_0

#define LU_INT_VECTOR_0   0x00000350

LU_INT_VECTOR_1

#define LU_INT_VECTOR_1   0x00000360

LU_IRR_0

#define LU_IRR_0   0x00000200

LU_ISR_0

#define LU_ISR_0   0x00000100

LU_PPR

#define LU_PPR   0x000000A0

LU_REMOTE_REGISTER

#define LU_REMOTE_REGISTER   0x000000C0

LU_SIZE

#define LU_SIZE   0x400

LU_SPURIOUS_VECTOR

#define LU_SPURIOUS_VECTOR   0x000000F0

LU_TIMER_VECTOR

#define LU_TIMER_VECTOR   0x00000320

LU_TMR_0

#define LU_TMR_0   0x00000180

LU_TPR

#define LU_TPR   0x00000080

LU_VERS_REGISTER

#define LU_VERS_REGISTER   0x00000030

SET_APIC_DELIVERY_MODE

#define SET_APIC_DELIVERY_MODE	(		x,
			y )

Value:

(((x) & ~0x700) | ((y) << 8))

SET_APIC_DEST_FIELD

#define SET_APIC_DEST_FIELD

(

x

)

Value:

((x) << 24)

SET_APIC_LOGICAL_ID

#define SET_APIC_LOGICAL_ID

(

x

)

Value:

(((x) << 24))

SET_APIC_TIMER_BASE

#define SET_APIC_TIMER_BASE

(

x

)

Value:

(((x) << 18))

TO_X2

#define TO_X2

(

x

)

Value:

(x / 0x10)

X2_MSR_BASE

#define X2_MSR_BASE   0x800

Typedef Documentation

IO_APIC_ENT

typedef struct _IO_APIC_ENT IO_APIC_ENT

PIO_APIC_ENT

typedef struct _IO_APIC_ENT * PIO_APIC_ENT

Function Documentation

ApicInitialize()

BOOLEAN ApicInitialize

(

)

Initialize APIC.

Returns

BOOLEAN

{
    UINT64           ApicBaseMSR;
    PHYSICAL_ADDRESS PaApicBase;
    PHYSICAL_ADDRESS PaIoApicBase;
 
    ApicBaseMSR = CpuReadMsr(IA32_APIC_BASE);
 
    if (!(ApicBaseMSR & (1 << 11)))
    {
        return FALSE;
    }
 
    //
    // Map I/O APIC default base address
    //
    // The exact APIC base address should be read from MADT table (ACPI)
    // However, we don't have an ACPI parser right now, but the address
    // is proved to stay at this (default) physical address since Intel
    // recommends OS/BIOS to not relocate it, but it could be relocated
    // however, this address is valid for almost all of the systems
    //
    PaIoApicBase.QuadPart = IO_APIC_DEFAULT_BASE_ADDR & 0xFFFFFF000;
    g_IoApicBase          = MmMapIoSpace(PaIoApicBase, 0x1000, MmNonCached);
 
    if (!g_IoApicBase)
    {
        //
        // Not gonna fail the initialization since the IOAPIC might be relocated by
        // either OS/BIOS
        //
 
        // return FALSE;
    }
 
    if (ApicBaseMSR & (1 << 10))
    {
        g_CompatibilityCheck.IsX2Apic = TRUE;
 
        return FALSE;
    }
    else
    {
        PaApicBase.QuadPart = ApicBaseMSR & 0xFFFFFF000;
        g_ApicBase          = MmMapIoSpace(PaApicBase, 0x1000, MmNonCached);
 
        if (!g_ApicBase)
        {
            return FALSE;
        }
 
        g_CompatibilityCheck.IsX2Apic = FALSE;
    }
 
    return TRUE;
}

ApicSelfIpi()

VOID ApicSelfIpi

(

UINT32

Vector

)

Self IPI the current core.

Parameters

Vector

Returns

VOID

{
    //
    // Check and apply self-IPI to x2APIC and xAPIC
    //
    if (g_CompatibilityCheck.IsX2Apic)
    {
        X2ApicIcrWrite(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | Vector, 0);
    }
    else
    {
        XApicIcrWrite(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | Vector, 0);
    }
}

ApicStoreIoApicFields()

BOOLEAN ApicStoreIoApicFields

(

IO_APIC_ENTRY_PACKETS *

IoApicPackets

)

Store the details of I/O APIC.

Parameters

IoApicPackets

Returns

BOOLEAN

{
    //
    // Dump I/O APIC Entries
    // Note that I/O APIC is not accessed through MSRs (e.g., X2APIC)
    // So, it's all about the physical memory
    //
    ApicDumpIoApic(IoApicPackets);
 
    //
    // There is not error defined for it at the moment
    //
    return TRUE;
}

ApicStoreLocalApicFields()

BOOLEAN ApicStoreLocalApicFields	(	PLAPIC_PAGE	LApicBuffer,
		PBOOLEAN	IsUsingX2APIC )

Store the details of APIC in xAPIC and x2APIC mode.

Parameters

LApicBuffer
IsUsingX2APIC

Returns

BOOLEAN

{
    if (g_CompatibilityCheck.IsX2Apic)
    {
        *IsUsingX2APIC = TRUE;
        return ApicStoreLocalApicInX2ApicMode(LApicBuffer);
    }
    else
    {
        *IsUsingX2APIC = FALSE;
        return ApicStoretLocalApicInXApicMode(LApicBuffer);
    }
}

ApicTriggerGenericNmi()

VOID ApicTriggerGenericNmi

(

)

Trigger NMI on X2APIC or APIC based on Current system.

Returns

VOID

{
    if (g_CompatibilityCheck.IsX2Apic)
    {
        X2ApicIcrWrite((4 << 8) | (1 << 14) | (3 << 18), 0);
    }
    else
    {
        XApicIcrWrite((4 << 8) | (1 << 14) | (3 << 18), 0);
    }
}

ApicUninitialize()

VOID ApicUninitialize

(

)

Uninitialize APIC.

Returns

VOID

{
    //
    // Unmap Local APIC base
    //
    if (g_ApicBase)
    {
        MmUnmapIoSpace(g_ApicBase, 0x1000);
    }
 
    //
    // Unmap I/O APIC base
    //
    if (g_IoApicBase)
    {
        MmUnmapIoSpace(g_IoApicBase, 0x1000);
    }
}