CompatibilityChecks.c File Reference

Checks for processor compatibility with different features. More...

#include "pch.h"

Functions
BOOLEAN	CompatibilityCheckCpuSupportForRtm ()
	Check whether the processor supports RTM or not.
UINT32	CompatibilityCheckGetX86VirtualAddressWidth ()
	Get virtual address width for x86 processors.
UINT32	CompatibilityCheckGetX86PhysicalAddressWidth ()
	Get physical address width for x86 processors.
BOOLEAN	CompatibilityCheckModeBasedExecution ()
	Check for mode-based execution.
BOOLEAN	CompatibilityCheckPml ()
	Check for Page Modification Logging (PML) support.
VOID	CompatibilityCheckPerformChecks ()
	Checks for the compatibility features based on current processor @detail NOTE: NOT ALL OF THE CHECKS ARE PERFORMED HERE.

Detailed Description

Checks for processor compatibility with different features.

Author

Sina Karvandi (sina@.nosp@m.hype.nosp@m.rdbg..nosp@m.org)

Version

0.2

Date

2023-03-15

Copyright

This project is released under the GNU Public License v3.

Function Documentation

CompatibilityCheckCpuSupportForRtm()

BOOLEAN CompatibilityCheckCpuSupportForRtm

(

)

Check whether the processor supports RTM or not.

Returns

BOOLEAN

{
    int     Regs1[4];
    int     Regs2[4];
    BOOLEAN Result;
 
    //
    // TSX is controlled via MSR_IA32_TSX_CTRL.  However, support for this
    // MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
    //
    // TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
    // microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
    // bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
    // MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
    // tsx= cmdline requests will do nothing on CPUs without
    // MSR_IA32_TSX_CTRL support.
    //
 
    CommonCpuidInstruction(0, 0, Regs1);
    CommonCpuidInstruction(7, 0, Regs2);
 
    //
    // Check RTM and MPX extensions in order to filter out TSX on Haswell CPUs
    //
    Result = Regs1[0] >= 0x7 && (Regs2[1] & 0x4800) == 0x4800;
 
    return Result;
}

CompatibilityCheckGetX86PhysicalAddressWidth()

UINT32 CompatibilityCheckGetX86PhysicalAddressWidth

(

)

Get physical address width for x86 processors.

Returns

UINT32

{
    int Regs[4];
 
    CommonCpuidInstruction(CPUID_ADDR_WIDTH, 0, Regs);
 
    //
    // Extracting bit 7:0 from eax register
    //
    return (Regs[0] & 0x0ff);
}

CompatibilityCheckGetX86VirtualAddressWidth()

UINT32 CompatibilityCheckGetX86VirtualAddressWidth

(

)

Get virtual address width for x86 processors.

Returns

UINT32

{
    int Regs[4];
 
    CommonCpuidInstruction(CPUID_ADDR_WIDTH, 0, Regs);
 
    //
    // Extracting bit 15:8 from eax register
    //
    return ((Regs[0] >> 8) & 0x0ff);
}

CompatibilityCheckModeBasedExecution()

BOOLEAN CompatibilityCheckModeBasedExecution

(

)

Check for mode-based execution.

Returns

BOOLEAN

{
    //
    // The PML address and PML index fields exist only on processors that support the 1-setting of
    // the "enable PML" VM - execution control
    //
    UINT32 SecondaryProcBasedVmExecControls = HvAdjustControls(IA32_VMX_PROCBASED_CTLS2_MODE_BASED_EXECUTE_CONTROL_FOR_EPT_FLAG,
                                                              IA32_VMX_PROCBASED_CTLS2);
 
    if (SecondaryProcBasedVmExecControls & IA32_VMX_PROCBASED_CTLS2_MODE_BASED_EXECUTE_CONTROL_FOR_EPT_FLAG)
    {
        //
        // The processor support PML
        //
        return TRUE;
    }
    else
    {
        //
        // Not supported
        //
        return FALSE;
    }
}

CompatibilityCheckPerformChecks()

VOID CompatibilityCheckPerformChecks

(

)

Checks for the compatibility features based on current processor @detail NOTE: NOT ALL OF THE CHECKS ARE PERFORMED HERE.

Returns

VOID

{
    //
    // Check if processor supports TSX (RTM)
    //
    g_CompatibilityCheck.RtmSupport = CompatibilityCheckCpuSupportForRtm();
 
    //
    // Get x86 processor width for virtual address
    //
    g_CompatibilityCheck.VirtualAddressWidth = CompatibilityCheckGetX86VirtualAddressWidth();
 
    //
    // Get x86 processor width for physical address
    //
    g_CompatibilityCheck.PhysicalAddressWidth = CompatibilityCheckGetX86PhysicalAddressWidth();
 
    //
    // Check Mode-based execution compatibility
    //
    g_CompatibilityCheck.ModeBasedExecutionSupport = CompatibilityCheckModeBasedExecution();
 
    //
    // Check PML support
    //
    g_CompatibilityCheck.PmlSupport = CompatibilityCheckPml();
 
    //
    // Log for testing
    //
    LogDebugInfo("Mode based execution: %s | PML: %s",
                 g_CompatibilityCheck.ModeBasedExecutionSupport ? "true" : "false",
                 g_CompatibilityCheck.PmlSupport ? "true" : "false");
}

CompatibilityCheckPml()

BOOLEAN CompatibilityCheckPml

(

)

Check for Page Modification Logging (PML) support.

Returns

BOOLEAN

{
    //
    // The PML address and PML index fields exist only on processors that support the 1-setting of
    // the "enable PML" VM - execution control
    //
    UINT32 SecondaryProcBasedVmExecControls = HvAdjustControls(IA32_VMX_PROCBASED_CTLS2_ENABLE_PML_FLAG, IA32_VMX_PROCBASED_CTLS2);
 
    if (SecondaryProcBasedVmExecControls & IA32_VMX_PROCBASED_CTLS2_ENABLE_PML_FLAG)
    {
        //
        // The processor support MBEC
        //
        return TRUE;
    }
    else
    {
        //
        // Not supported
        //
        return FALSE;
    }
}