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Classes | |
| struct | hv_gpa_range_for_visibility |
| union | hv_x64_msr_hypercall_contents |
| union | hv_vp_assist_msr_contents |
| struct | hv_reenlightenment_control |
| struct | hv_tsc_emulation_control |
| struct | hv_tsc_emulation_status |
| struct | hv_nested_enlightenments_control |
| struct | hv_vp_assist_page |
| struct | hv_enlightened_vmcs |
| struct | hv_partition_assist_pg |
| union | hv_msi_address_register |
| union | hv_msi_data_register |
| union | hv_msi_entry |
Enumerations | |
| enum | hv_isolation_type { HV_ISOLATION_TYPE_NONE = 0 , HV_ISOLATION_TYPE_VBS = 1 , HV_ISOLATION_TYPE_SNP = 2 } |
| enum | hv_mem_host_visibility { VMBUS_PAGE_NOT_VISIBLE = 0 , VMBUS_PAGE_VISIBLE_READ_ONLY = 1 , VMBUS_PAGE_VISIBLE_READ_WRITE = 3 } |
| enum | hv_interrupt_type { HV_X64_INTERRUPT_TYPE_FIXED = 0x0000 , HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001 , HV_X64_INTERRUPT_TYPE_SMI = 0x0002 , HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003 , HV_X64_INTERRUPT_TYPE_NMI = 0x0004 , HV_X64_INTERRUPT_TYPE_INIT = 0x0005 , HV_X64_INTERRUPT_TYPE_SIPI = 0x0006 , HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007 , HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008 , HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009 , HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A } |
Variables | |
| struct hv_gpa_range_for_visibility | __packed |
| #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) |
| #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) |
| #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) |
| #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) |
| #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 |
| #define HV_IPI_HIGH_VECTOR 0xff |
| #define HV_IPI_LOW_VECTOR 0x10 |
| #define HV_ISOLATION_TYPE GENMASK(3, 0) |
| #define HV_PARAVISOR_PRESENT BIT(0) |
| #define HV_REGISTER_CRASH_CTL 0x40000105 |
| #define HV_REGISTER_CRASH_P0 0x40000100 |
| #define HV_REGISTER_CRASH_P1 0x40000101 |
| #define HV_REGISTER_CRASH_P2 0x40000102 |
| #define HV_REGISTER_CRASH_P3 0x40000103 |
| #define HV_REGISTER_CRASH_P4 0x40000104 |
| #define HV_REGISTER_EOM 0x40000084 |
| #define HV_REGISTER_REFERENCE_TSC 0x40000021 |
| #define HV_REGISTER_SCONTROL 0x40000080 |
| #define HV_REGISTER_SIEFP 0x40000082 |
| #define HV_REGISTER_SIMP 0x40000083 |
| #define HV_REGISTER_SINT0 0x40000090 |
| #define HV_REGISTER_SINT1 0x40000091 |
| #define HV_REGISTER_SINT10 0x4000009A |
| #define HV_REGISTER_SINT11 0x4000009B |
| #define HV_REGISTER_SINT12 0x4000009C |
| #define HV_REGISTER_SINT13 0x4000009D |
| #define HV_REGISTER_SINT14 0x4000009E |
| #define HV_REGISTER_SINT15 0x4000009F |
| #define HV_REGISTER_SINT2 0x40000092 |
| #define HV_REGISTER_SINT3 0x40000093 |
| #define HV_REGISTER_SINT4 0x40000094 |
| #define HV_REGISTER_SINT5 0x40000095 |
| #define HV_REGISTER_SINT6 0x40000096 |
| #define HV_REGISTER_SINT7 0x40000097 |
| #define HV_REGISTER_SINT8 0x40000098 |
| #define HV_REGISTER_SINT9 0x40000099 |
| #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 |
| #define HV_REGISTER_STIMER0_COUNT 0x400000B1 |
| #define HV_REGISTER_STIMER1_CONFIG 0x400000B2 |
| #define HV_REGISTER_STIMER1_COUNT 0x400000B3 |
| #define HV_REGISTER_STIMER2_CONFIG 0x400000B4 |
| #define HV_REGISTER_STIMER2_COUNT 0x400000B5 |
| #define HV_REGISTER_STIMER3_CONFIG 0x400000B6 |
| #define HV_REGISTER_STIMER3_COUNT 0x400000B7 |
| #define HV_REGISTER_SVERSION 0x40000081 |
| #define HV_REGISTER_TIME_REF_COUNT 0x40000020 |
| #define HV_REGISTER_VP_INDEX 0x40000002 |
| #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) |
| #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) |
| #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) |
| #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 |
| #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) |
| #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) |
| #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) |
| #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) |
| #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) |
| #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) |
| #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff |
| #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) |
| #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) |
| #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) |
| #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) |
| #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) |
| #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) |
| #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 |
| #define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL |
| #define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0 |
| #define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1 |
| #define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2 |
| #define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3 |
| #define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4 |
| #define HV_X64_MSR_CRASH_PARAMS (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) |
| #define HV_X64_MSR_EOI 0x40000070 |
| #define HV_X64_MSR_EOM HV_REGISTER_EOM |
| #define HV_X64_MSR_GUEST_IDLE 0x400000F0 |
| #define HV_X64_MSR_GUEST_OS_ID 0x40000000 |
| #define HV_X64_MSR_HYPERCALL 0x40000001 |
| #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 |
| #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) |
| #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 |
| #define HV_X64_MSR_ICR 0x40000071 |
| #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 |
| #define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC |
| #define HV_X64_MSR_RESET 0x40000003 |
| #define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL |
| #define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP |
| #define HV_X64_MSR_SIMP HV_REGISTER_SIMP |
| #define HV_X64_MSR_SINT0 HV_REGISTER_SINT0 |
| #define HV_X64_MSR_SINT15 HV_REGISTER_SINT15 |
| #define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG |
| #define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT |
| #define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG |
| #define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT |
| #define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG |
| #define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT |
| #define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG |
| #define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT |
| #define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION |
| #define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT |
| #define HV_X64_MSR_TPR 0x40000072 |
| #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 |
| #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 |
| #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 |
| #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 |
| #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 |
| #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 |
| #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 |
| #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) |
| #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 |
| #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 |
| #define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX |
| #define HV_X64_MSR_VP_RUNTIME 0x40000010 |
| #define HV_X64_MWAIT_AVAILABLE BIT(0) |
| #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) |
| #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) |
| #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) |
| #define HV_X64_NESTED_MSR_BITMAP BIT(19) |
| #define HV_X64_NO_NONARCH_CORESHARING BIT(18) |
| #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) |
| #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) |
| #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) |
| #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) |
| #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) |
| #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) |
| #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) |
| #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 |
| #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 |
| #define HYPERV_CPUID_FEATURES 0x40000003 |
| #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 |
| #define HYPERV_CPUID_INTERFACE 0x40000001 |
| #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C |
| #define HYPERV_CPUID_MAX 0x4000ffff |
| #define HYPERV_CPUID_MIN 0x40000005 |
| #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A |
| #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 |
| #define HYPERV_CPUID_VERSION 0x40000002 |
| #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 |
| #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 |
| #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 |
| #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ |
| #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) |
| enum hv_interrupt_type |
| enum hv_isolation_type |
| Enumerator | |
|---|---|
| HV_ISOLATION_TYPE_NONE | |
| HV_ISOLATION_TYPE_VBS | |
| HV_ISOLATION_TYPE_SNP | |
| Enumerator | |
|---|---|
| VMBUS_PAGE_NOT_VISIBLE | |
| VMBUS_PAGE_VISIBLE_READ_ONLY | |
| VMBUS_PAGE_VISIBLE_READ_WRITE | |
| struct hv_gpa_range_for_visibility __packed |
1.11.0