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Macros | Functions | Variables
msm8974.c File Reference
#include "common.h"

Macros

#define UART_RX_BYTES_TO_RECEIVE   0x2000
 
#define RX_FIFO_WIDTH   sizeof(UINT32)
 
#define UART_DM_MR1_ADDR   0x00000000
 
#define UART_DM_MR2_ADDR   0x00000004
 
#define UART_DM_IPR_ADDR   0x00000018
 
#define UART_DM_TFWR_ADDR   0x0000001c
 
#define UART_DM_RFWR_ADDR   0x00000020
 
#define UART_DM_HCR_ADDR   0x00000024
 
#define UART_DM_DMRX_ADDR   0x00000034
 
#define UART_DM_IRDA_ADDR   0x00000038
 
#define UART_DM_DMEN_ADDR   0x0000003c
 
#define UART_DM_NO_CHARS_FOR_TX_ADDR   0x00000040
 
#define UART_DM_BADR_ADDR   0x00000044
 
#define UART_DM_TXFS_ADDR   0x0000004c
 
#define UART_DM_RXFS_ADDR   0x00000050
 
#define UART_DM_CSR_ADDR   0x000000A0
 
#define UART_DM_SR_ADDR   0x000000A4
 
#define UART_DM_CR_ADDR   0x000000A8
 
#define UART_DM_IMR_ADDR   0x000000B0
 
#define UART_DM_ISR_ADDR   0x000000B4
 
#define UART_DM_RX_TOTAL_SNAP_ADDR   0x000000BC
 
#define UART_DM_TF_ADDR   0x00000100
 
#define UART_DM_RF_ADDR   0x00000140
 
#define UART_DM_MR1_RFRC   0x80
 
#define UART_DM_MR1_CTSC   0x40
 
#define UART_DM_MR2_LOOPBACK   0x80
 
#define UART_DM_MR2_ERRMODE   0x40
 
#define UART_DM_MR2_5BPC   0x00
 
#define UART_DM_MR2_6BPC   0x10
 
#define UART_DM_MR2_7BPC   0x20
 
#define UART_DM_MR2_8BPC   0x30
 
#define UART_DM_MR2_05SB   0x00
 
#define UART_DM_MR2_1SB   0x04
 
#define UART_DM_MR2_15SB   0x08
 
#define UART_DM_MR2_2SB   0x0C
 
#define UART_DM_MR2_NOPAR   0x00
 
#define UART_DM_MR2_OPAR   0x01
 
#define UART_DM_MR2_EPAR   0x02
 
#define UART_DM_MR2_SPAR   0x03
 
#define UART_DM_SR_RXRDY_BMSK   0x1
 
#define UART_DM_SR_TXRDY_BMSK   0x4
 
#define UART_DM_SR_TXEMT_BMSK   0x8
 
#define UART_DM_SR_UART_OVERRUN_BMSK   0x10
 
#define UART_DM_SR_PAR_FRAME_ERR_BMSK   0x20
 
#define UART_DM_SR_RX_BREAK_BMSK   0x40
 
#define UART_DM_SR_HUNT_CHAR_BMSK   0x80
 
#define UART_DM_SR_ERROR_BMSK
 
#define UART_DM_ISR_RXSTALE_BMSK   0x8
 
#define UART_DM_ISR_TX_READY_BMSK   0x80
 
#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK   0x7f
 
#define UART_DM_DMA_EN_RXTX_DM_DIS   0x00
 
#define UART_DM_CR_ENA_RX   0x01
 
#define UART_DM_CR_DIS_RX   0x02
 
#define UART_DM_CR_ENA_TX   0x04
 
#define UART_DM_CR_DIS_TX   0x08
 
#define UART_DM_CR_NULL_CMD   0x0000
 
#define UART_DM_CR_RESET_RX   0x0010
 
#define UART_DM_CR_RESET_TX   0x0020
 
#define UART_DM_CR_RESET_ERR   0x0030
 
#define UART_DM_CR_RESET_BRK_INT   0x0040
 
#define UART_DM_CR_STA_BRK   0x0050
 
#define UART_DM_CR_STO_BRK   0x0060
 
#define UART_DM_CR_CLR_DCTS   0x0070
 
#define UART_DM_CR_RESET_STALE   0x0080
 
#define UART_DM_CR_SAMP_MODE   0x0090
 
#define UART_DM_CR_TEST_PARITY   0x00A0
 
#define UART_DM_CR_TEST_FRAME   0x00B0
 
#define UART_DM_CR_RESET_SAMPLE   0x00C0
 
#define UART_DM_CR_SET_RFR   0x00D0
 
#define UART_DM_CR_RESET_RFR   0x00E0
 
#define UART_DM_CR_RESET_TX_ERR   0x0800
 
#define UART_DM_CR_RESET_TX_DONE   0x0810
 
#define UART_DM_CR_ENA_CR_PROT   0x0100
 
#define UART_DM_CR_DIS_CR_PROT   0x0200
 
#define UART_DM_CR_RESET_TX_RDY   0x0300
 
#define UART_DM_CR_FORCE_STALE   0x0400
 
#define UART_DM_CR_ENA_STALE_EVT   0x0500
 
#define UART_DM_CR_DIS_STALE_EVT   0x0600
 
#define UART_DM_IMR_TX_DONE   0x200
 
#define UART_DM_IMR_TX_ERROR   0x100
 
#define UART_DM_IMR_TX_READY   0x080
 
#define UART_DM_IMR_CUR_CTS   0x040
 
#define UART_DM_IMR_DELTA_CTS   0x020
 
#define UART_DM_IMR_RXLEV   0x010
 
#define UART_DM_IMR_RXSTALE   0x008
 
#define UART_DM_IMR_RXBREAK   0x004
 
#define UART_DM_IMR_RXHUNT   0x002
 
#define UART_DM_IMR_TXLEV   0x001
 
#define UART_DM_IMR_NONE   0x000
 
#define UART_DM_MR1_DEFAULT   0
 
#define UART_DM_MR2_DEFAULT
 
#define UART_DM_IMR_DEFAULT   0
 
#define UART_DM_IPR_DEFAULT   0x2
 
#define UART_DM_BADR_DEFAULT   0x70
 
#define UART_DM_IRDA_DISABLE   0x00
 
#define UART_DM_CH_CMD_RESET_RECEIVER   0x01
 
#define UART_DM_CH_CMD_RESET_TRANSMITTER   0x02
 
#define UART_DM_CH_CMD_RESET_ERROR_STATUS   0x03
 
#define UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ   0x04
 
#define UART_DM_CH_CMD_START_BREAK   0x05
 
#define UART_DM_CH_CMD_STOP_BREAK   0x06
 
#define UART_DM_CH_CMD_RESET_CTS_N   0x07
 
#define UART_DM_CH_CMD_RESET_STALE_IRQ   0x08
 
#define UART_DM_CH_CMD_PACKET_MODE   0x09
 
#define UART_DM_CH_CMD_TEST_PARITY_ON   0x0A
 
#define UART_DM_CH_CMD_TEST_FRAME_ON   0x0B
 
#define UART_DM_CH_CMD_MODE_RESET   0x0C
 
#define UART_DM_CH_CMD_SET_RFR_N   0x0D
 
#define UART_DM_CH_CMD_RESET_RFR_N   0x0E
 
#define UART_DM_CH_CMD_UART_RESET_INT   0x0F
 
#define UART_DM_CH_CMD_RESET_TX_ERROR   0x10
 
#define UART_DM_CH_CMD_CLEAR_TX_DONE   0x11
 
#define UART_DM_CH_CMD_RESET_BRK_START_IRQ   0x12
 
#define UART_DM_CH_CMD_RESET_BRK_END_IRQ   0x13
 
#define UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ   0x14
 
#define UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE   0x01
 
#define UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE   0x02
 
#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ   0x03
 
#define UART_DM_GENERAL_CMD_SW_FORCE_STALE   0x04
 
#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT   0x05
 
#define UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT   0x06
 
#define UART_DM_READ_REG(addr, offset)    READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))
 
#define UART_DM_WRITE_REG(addr, offset, val)    WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)
 
#define UART_DM_CH_CMD(a, v)
 
#define UART_DM_GENERAL_CMD(a, v)    UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)
 

Functions

BOOLEAN MSM8974SetBaud (_Inout_ PCPPORT Port, ULONG Rate)
 
BOOLEAN MSM8974InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
 
UART_STATUS MSM8974GetByte (_Inout_ PCPPORT Port, _Out_ PUCHAR Byte)
 
UART_STATUS MSM8974PutByte (_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait)
 
BOOLEAN MSM8974RxReady (_Inout_ PCPPORT Port)
 

Variables

UART_HARDWARE_DRIVER MSM8974HardwareDriver
 

Macro Definition Documentation

◆ RX_FIFO_WIDTH

#define RX_FIFO_WIDTH   sizeof(UINT32)

◆ UART_DM_BADR_ADDR

#define UART_DM_BADR_ADDR   0x00000044

◆ UART_DM_BADR_DEFAULT

#define UART_DM_BADR_DEFAULT   0x70

◆ UART_DM_CH_CMD

#define UART_DM_CH_CMD ( a,
v )
Value:
UART_DM_WRITE_REG((a), \
UART_DM_CR_ADDR, \
((((v) >> 4) & 0x1) << 11) | (((v) & 0xF) << 4))
UART_DM_WRITE_REG
#define UART_DM_WRITE_REG(addr, offset, val)
Definition msm8974.c:226
UART_DM_CR_ADDR
#define UART_DM_CR_ADDR
Definition msm8974.c:43
229#define UART_DM_CH_CMD(a, v) \
230 UART_DM_WRITE_REG((a), \
231 UART_DM_CR_ADDR, \
232 ((((v) >> 4) & 0x1) << 11) | (((v) & 0xF) << 4))

◆ UART_DM_CH_CMD_CLEAR_TX_DONE

#define UART_DM_CH_CMD_CLEAR_TX_DONE   0x11

◆ UART_DM_CH_CMD_MODE_RESET

#define UART_DM_CH_CMD_MODE_RESET   0x0C

◆ UART_DM_CH_CMD_PACKET_MODE

#define UART_DM_CH_CMD_PACKET_MODE   0x09

◆ UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ

#define UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ   0x04

◆ UART_DM_CH_CMD_RESET_BRK_END_IRQ

#define UART_DM_CH_CMD_RESET_BRK_END_IRQ   0x13

◆ UART_DM_CH_CMD_RESET_BRK_START_IRQ

#define UART_DM_CH_CMD_RESET_BRK_START_IRQ   0x12

◆ UART_DM_CH_CMD_RESET_CTS_N

#define UART_DM_CH_CMD_RESET_CTS_N   0x07

◆ UART_DM_CH_CMD_RESET_ERROR_STATUS

#define UART_DM_CH_CMD_RESET_ERROR_STATUS   0x03

◆ UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ

#define UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ   0x14

◆ UART_DM_CH_CMD_RESET_RECEIVER

#define UART_DM_CH_CMD_RESET_RECEIVER   0x01

◆ UART_DM_CH_CMD_RESET_RFR_N

#define UART_DM_CH_CMD_RESET_RFR_N   0x0E

◆ UART_DM_CH_CMD_RESET_STALE_IRQ

#define UART_DM_CH_CMD_RESET_STALE_IRQ   0x08

◆ UART_DM_CH_CMD_RESET_TRANSMITTER

#define UART_DM_CH_CMD_RESET_TRANSMITTER   0x02

◆ UART_DM_CH_CMD_RESET_TX_ERROR

#define UART_DM_CH_CMD_RESET_TX_ERROR   0x10

◆ UART_DM_CH_CMD_SET_RFR_N

#define UART_DM_CH_CMD_SET_RFR_N   0x0D

◆ UART_DM_CH_CMD_START_BREAK

#define UART_DM_CH_CMD_START_BREAK   0x05

◆ UART_DM_CH_CMD_STOP_BREAK

#define UART_DM_CH_CMD_STOP_BREAK   0x06

◆ UART_DM_CH_CMD_TEST_FRAME_ON

#define UART_DM_CH_CMD_TEST_FRAME_ON   0x0B

◆ UART_DM_CH_CMD_TEST_PARITY_ON

#define UART_DM_CH_CMD_TEST_PARITY_ON   0x0A

◆ UART_DM_CH_CMD_UART_RESET_INT

#define UART_DM_CH_CMD_UART_RESET_INT   0x0F

◆ UART_DM_CR_ADDR

#define UART_DM_CR_ADDR   0x000000A8

◆ UART_DM_CR_CLR_DCTS

#define UART_DM_CR_CLR_DCTS   0x0070

◆ UART_DM_CR_DIS_CR_PROT

#define UART_DM_CR_DIS_CR_PROT   0x0200

◆ UART_DM_CR_DIS_RX

#define UART_DM_CR_DIS_RX   0x02

◆ UART_DM_CR_DIS_STALE_EVT

#define UART_DM_CR_DIS_STALE_EVT   0x0600

◆ UART_DM_CR_DIS_TX

#define UART_DM_CR_DIS_TX   0x08

◆ UART_DM_CR_ENA_CR_PROT

#define UART_DM_CR_ENA_CR_PROT   0x0100

◆ UART_DM_CR_ENA_RX

#define UART_DM_CR_ENA_RX   0x01

◆ UART_DM_CR_ENA_STALE_EVT

#define UART_DM_CR_ENA_STALE_EVT   0x0500

◆ UART_DM_CR_ENA_TX

#define UART_DM_CR_ENA_TX   0x04

◆ UART_DM_CR_FORCE_STALE

#define UART_DM_CR_FORCE_STALE   0x0400

◆ UART_DM_CR_NULL_CMD

#define UART_DM_CR_NULL_CMD   0x0000

◆ UART_DM_CR_RESET_BRK_INT

#define UART_DM_CR_RESET_BRK_INT   0x0040

◆ UART_DM_CR_RESET_ERR

#define UART_DM_CR_RESET_ERR   0x0030

◆ UART_DM_CR_RESET_RFR

#define UART_DM_CR_RESET_RFR   0x00E0

◆ UART_DM_CR_RESET_RX

#define UART_DM_CR_RESET_RX   0x0010

◆ UART_DM_CR_RESET_SAMPLE

#define UART_DM_CR_RESET_SAMPLE   0x00C0

◆ UART_DM_CR_RESET_STALE

#define UART_DM_CR_RESET_STALE   0x0080

◆ UART_DM_CR_RESET_TX

#define UART_DM_CR_RESET_TX   0x0020

◆ UART_DM_CR_RESET_TX_DONE

#define UART_DM_CR_RESET_TX_DONE   0x0810

◆ UART_DM_CR_RESET_TX_ERR

#define UART_DM_CR_RESET_TX_ERR   0x0800

◆ UART_DM_CR_RESET_TX_RDY

#define UART_DM_CR_RESET_TX_RDY   0x0300

◆ UART_DM_CR_SAMP_MODE

#define UART_DM_CR_SAMP_MODE   0x0090

◆ UART_DM_CR_SET_RFR

#define UART_DM_CR_SET_RFR   0x00D0

◆ UART_DM_CR_STA_BRK

#define UART_DM_CR_STA_BRK   0x0050

◆ UART_DM_CR_STO_BRK

#define UART_DM_CR_STO_BRK   0x0060

◆ UART_DM_CR_TEST_FRAME

#define UART_DM_CR_TEST_FRAME   0x00B0

◆ UART_DM_CR_TEST_PARITY

#define UART_DM_CR_TEST_PARITY   0x00A0

◆ UART_DM_CSR_ADDR

#define UART_DM_CSR_ADDR   0x000000A0

◆ UART_DM_DMA_EN_RXTX_DM_DIS

#define UART_DM_DMA_EN_RXTX_DM_DIS   0x00

◆ UART_DM_DMEN_ADDR

#define UART_DM_DMEN_ADDR   0x0000003c

◆ UART_DM_DMRX_ADDR

#define UART_DM_DMRX_ADDR   0x00000034

◆ UART_DM_GENERAL_CMD

#define UART_DM_GENERAL_CMD ( a,
v )    UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)
233#define UART_DM_GENERAL_CMD(a, v) \
234 UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)

◆ UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE

#define UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE   0x02

◆ UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE

#define UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE   0x01

◆ UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT

#define UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT   0x06

◆ UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT

#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT   0x05

◆ UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ

#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ   0x03

◆ UART_DM_GENERAL_CMD_SW_FORCE_STALE

#define UART_DM_GENERAL_CMD_SW_FORCE_STALE   0x04

◆ UART_DM_HCR_ADDR

#define UART_DM_HCR_ADDR   0x00000024

◆ UART_DM_IMR_ADDR

#define UART_DM_IMR_ADDR   0x000000B0

◆ UART_DM_IMR_CUR_CTS

#define UART_DM_IMR_CUR_CTS   0x040

◆ UART_DM_IMR_DEFAULT

#define UART_DM_IMR_DEFAULT   0

◆ UART_DM_IMR_DELTA_CTS

#define UART_DM_IMR_DELTA_CTS   0x020

◆ UART_DM_IMR_NONE

#define UART_DM_IMR_NONE   0x000

◆ UART_DM_IMR_RXBREAK

#define UART_DM_IMR_RXBREAK   0x004

◆ UART_DM_IMR_RXHUNT

#define UART_DM_IMR_RXHUNT   0x002

◆ UART_DM_IMR_RXLEV

#define UART_DM_IMR_RXLEV   0x010

◆ UART_DM_IMR_RXSTALE

#define UART_DM_IMR_RXSTALE   0x008

◆ UART_DM_IMR_TX_DONE

#define UART_DM_IMR_TX_DONE   0x200

◆ UART_DM_IMR_TX_ERROR

#define UART_DM_IMR_TX_ERROR   0x100

◆ UART_DM_IMR_TX_READY

#define UART_DM_IMR_TX_READY   0x080

◆ UART_DM_IMR_TXLEV

#define UART_DM_IMR_TXLEV   0x001

◆ UART_DM_IPR_ADDR

#define UART_DM_IPR_ADDR   0x00000018

◆ UART_DM_IPR_DEFAULT

#define UART_DM_IPR_DEFAULT   0x2

◆ UART_DM_IRDA_ADDR

#define UART_DM_IRDA_ADDR   0x00000038

◆ UART_DM_IRDA_DISABLE

#define UART_DM_IRDA_DISABLE   0x00

◆ UART_DM_ISR_ADDR

#define UART_DM_ISR_ADDR   0x000000B4

◆ UART_DM_ISR_RXSTALE_BMSK

#define UART_DM_ISR_RXSTALE_BMSK   0x8

◆ UART_DM_ISR_TX_READY_BMSK

#define UART_DM_ISR_TX_READY_BMSK   0x80

◆ UART_DM_MR1_ADDR

#define UART_DM_MR1_ADDR   0x00000000

◆ UART_DM_MR1_CTSC

#define UART_DM_MR1_CTSC   0x40

◆ UART_DM_MR1_DEFAULT

#define UART_DM_MR1_DEFAULT   0

◆ UART_DM_MR1_RFRC

#define UART_DM_MR1_RFRC   0x80

◆ UART_DM_MR2_05SB

#define UART_DM_MR2_05SB   0x00

◆ UART_DM_MR2_15SB

#define UART_DM_MR2_15SB   0x08

◆ UART_DM_MR2_1SB

#define UART_DM_MR2_1SB   0x04

◆ UART_DM_MR2_2SB

#define UART_DM_MR2_2SB   0x0C

◆ UART_DM_MR2_5BPC

#define UART_DM_MR2_5BPC   0x00

◆ UART_DM_MR2_6BPC

#define UART_DM_MR2_6BPC   0x10

◆ UART_DM_MR2_7BPC

#define UART_DM_MR2_7BPC   0x20

◆ UART_DM_MR2_8BPC

#define UART_DM_MR2_8BPC   0x30

◆ UART_DM_MR2_ADDR

#define UART_DM_MR2_ADDR   0x00000004

◆ UART_DM_MR2_DEFAULT

#define UART_DM_MR2_DEFAULT
Value:
(UART_DM_MR2_8BPC | \
UART_DM_MR2_1SB | \
UART_DM_MR2_NOPAR)
UART_DM_MR2_1SB
#define UART_DM_MR2_1SB
Definition msm8974.c:72
UART_DM_MR2_NOPAR
#define UART_DM_MR2_NOPAR
Definition msm8974.c:75
UART_DM_MR2_8BPC
#define UART_DM_MR2_8BPC
Definition msm8974.c:70
162#define UART_DM_MR2_DEFAULT (UART_DM_MR2_8BPC | \
163 UART_DM_MR2_1SB | \
164 UART_DM_MR2_NOPAR)

◆ UART_DM_MR2_EPAR

#define UART_DM_MR2_EPAR   0x02

◆ UART_DM_MR2_ERRMODE

#define UART_DM_MR2_ERRMODE   0x40

◆ UART_DM_MR2_LOOPBACK

#define UART_DM_MR2_LOOPBACK   0x80

◆ UART_DM_MR2_NOPAR

#define UART_DM_MR2_NOPAR   0x00

◆ UART_DM_MR2_OPAR

#define UART_DM_MR2_OPAR   0x01

◆ UART_DM_MR2_SPAR

#define UART_DM_MR2_SPAR   0x03

◆ UART_DM_NO_CHARS_FOR_TX_ADDR

#define UART_DM_NO_CHARS_FOR_TX_ADDR   0x00000040

◆ UART_DM_READ_REG

#define UART_DM_READ_REG ( addr,
offset )    READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))
223#define UART_DM_READ_REG(addr, offset) \
224 READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))

◆ UART_DM_RF_ADDR

#define UART_DM_RF_ADDR   0x00000140

◆ UART_DM_RFWR_ADDR

#define UART_DM_RFWR_ADDR   0x00000020

◆ UART_DM_RX_TOTAL_SNAP_ADDR

#define UART_DM_RX_TOTAL_SNAP_ADDR   0x000000BC

◆ UART_DM_RXFS_ADDR

#define UART_DM_RXFS_ADDR   0x00000050

◆ UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK

#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK   0x7f

◆ UART_DM_SR_ADDR

#define UART_DM_SR_ADDR   0x000000A4

◆ UART_DM_SR_ERROR_BMSK

#define UART_DM_SR_ERROR_BMSK
Value:
(UART_DM_SR_UART_OVERRUN_BMSK | \
UART_DM_SR_PAR_FRAME_ERR_BMSK)
UART_DM_SR_PAR_FRAME_ERR_BMSK
#define UART_DM_SR_PAR_FRAME_ERR_BMSK
Definition msm8974.c:88
UART_DM_SR_UART_OVERRUN_BMSK
#define UART_DM_SR_UART_OVERRUN_BMSK
Definition msm8974.c:87
91#define UART_DM_SR_ERROR_BMSK (UART_DM_SR_UART_OVERRUN_BMSK | \
92 UART_DM_SR_PAR_FRAME_ERR_BMSK)

◆ UART_DM_SR_HUNT_CHAR_BMSK

#define UART_DM_SR_HUNT_CHAR_BMSK   0x80

◆ UART_DM_SR_PAR_FRAME_ERR_BMSK

#define UART_DM_SR_PAR_FRAME_ERR_BMSK   0x20

◆ UART_DM_SR_RX_BREAK_BMSK

#define UART_DM_SR_RX_BREAK_BMSK   0x40

◆ UART_DM_SR_RXRDY_BMSK

#define UART_DM_SR_RXRDY_BMSK   0x1

◆ UART_DM_SR_TXEMT_BMSK

#define UART_DM_SR_TXEMT_BMSK   0x8

◆ UART_DM_SR_TXRDY_BMSK

#define UART_DM_SR_TXRDY_BMSK   0x4

◆ UART_DM_SR_UART_OVERRUN_BMSK

#define UART_DM_SR_UART_OVERRUN_BMSK   0x10

◆ UART_DM_TF_ADDR

#define UART_DM_TF_ADDR   0x00000100

◆ UART_DM_TFWR_ADDR

#define UART_DM_TFWR_ADDR   0x0000001c

◆ UART_DM_TXFS_ADDR

#define UART_DM_TXFS_ADDR   0x0000004c

◆ UART_DM_WRITE_REG

#define UART_DM_WRITE_REG ( addr,
offset,
val )    WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)
226#define UART_DM_WRITE_REG(addr, offset, val) \
227 WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)

◆ UART_RX_BYTES_TO_RECEIVE

#define UART_RX_BYTES_TO_RECEIVE   0x2000

Function Documentation

◆ MSM8974GetByte()

UART_STATUS MSM8974GetByte ( _Inout_ PCPPORT Port,
_Out_ PUCHAR Byte )
438{
439 static UINT32 RxWord;
440 static UINT32 Queued = 0;
441 static UINT32 Read = 0;
442 static UINT32 Snap = 0;
443
444 ULONG limitcount;
445
446 *Byte = 0;
447
448 if ((Port == NULL) || (Port->Address == NULL))
449 {
450 return UartNotReady;
451 }
452
453 if (Queued == 0)
454 {
455 PUCHAR Address = Port->Address;
456 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
457 UART_DM_SR_ERROR_BMSK) != 0)
458 {
459 UART_DM_CH_CMD(Address, UART_DM_CH_CMD_RESET_ERROR_STATUS);
460 }
461
462 limitcount = 1;
463 while (limitcount-- != 0)
464 {
465 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
466 UART_DM_SR_RXRDY_BMSK) == 0)
467 {
468 continue;
469 }
470
471 //
472 // Read only if there are more than 4 bytes in the FIFO or RX Stale
473 // occurred
474 //
475
476 if ((UART_DM_READ_REG(Address, UART_DM_RXFS_ADDR) &
477 UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK) == 1)
478 {
479 if ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
480 UART_DM_ISR_RXSTALE_BMSK) == 0)
481 {
482 continue;
483 }
484 }
485
486 RxWord = UART_DM_READ_REG(Address, UART_DM_RF_ADDR);
487 Queued = RX_FIFO_WIDTH;
488 Read += RX_FIFO_WIDTH;
489
490 if (Snap == 0)
491 {
492 if (UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
493 UART_DM_ISR_RXSTALE_BMSK)
494 {
495 Snap = UART_DM_READ_REG(Address,
496 UART_DM_RX_TOTAL_SNAP_ADDR);
497 }
498 }
499
500 if (Snap != 0)
501 {
502 if (Snap <= Read)
503 {
504 if (Snap + RX_FIFO_WIDTH > Read)
505 {
506 Queued = Snap + RX_FIFO_WIDTH - Read;
507 }
508 else
509 {
510 Queued = 0;
511 }
512
513 Read = 0;
514 Snap = 0;
515 UART_DM_CH_CMD(Address, UART_DM_CH_CMD_RESET_STALE_IRQ);
516 UART_DM_WRITE_REG(Address,
517 UART_DM_DMRX_ADDR,
518 UART_RX_BYTES_TO_RECEIVE);
519
520 UART_DM_GENERAL_CMD(Address,
521 UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT);
522 }
523 }
524
525 break;
526 }
527 }
528
529 if (Queued != 0)
530 {
531 *Byte = (int)(RxWord & 0xFF);
532 RxWord = RxWord >> 8;
533 Queued -= 1;
534 return UartSuccess;
535 }
536
537 return UartNoData;
538}
UINT32
unsigned int UINT32
Definition BasicTypes.h:48
ULONG
unsigned long ULONG
Definition BasicTypes.h:37
Address
UINT64 Address
Definition HyperDbgScriptImports.h:67
UART_DM_READ_REG
#define UART_DM_READ_REG(addr, offset)
Definition msm8974.c:223
UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT
#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT
Definition msm8974.c:218
UART_DM_CH_CMD_RESET_STALE_IRQ
#define UART_DM_CH_CMD_RESET_STALE_IRQ
Definition msm8974.c:196
UART_DM_RXFS_ADDR
#define UART_DM_RXFS_ADDR
Definition msm8974.c:40
UART_DM_ISR_RXSTALE_BMSK
#define UART_DM_ISR_RXSTALE_BMSK
Definition msm8974.c:98
UART_DM_CH_CMD
#define UART_DM_CH_CMD(a, v)
Definition msm8974.c:229
UART_DM_SR_RXRDY_BMSK
#define UART_DM_SR_RXRDY_BMSK
Definition msm8974.c:84
UART_DM_CH_CMD_RESET_ERROR_STATUS
#define UART_DM_CH_CMD_RESET_ERROR_STATUS
Definition msm8974.c:191
UART_DM_SR_ERROR_BMSK
#define UART_DM_SR_ERROR_BMSK
Definition msm8974.c:91
UART_DM_DMRX_ADDR
#define UART_DM_DMRX_ADDR
Definition msm8974.c:34
UART_DM_ISR_ADDR
#define UART_DM_ISR_ADDR
Definition msm8974.c:45
UART_RX_BYTES_TO_RECEIVE
#define UART_RX_BYTES_TO_RECEIVE
Definition msm8974.c:21
RX_FIFO_WIDTH
#define RX_FIFO_WIDTH
Definition msm8974.c:22
UART_DM_RF_ADDR
#define UART_DM_RF_ADDR
Definition msm8974.c:48
UART_DM_SR_ADDR
#define UART_DM_SR_ADDR
Definition msm8974.c:42
UART_DM_RX_TOTAL_SNAP_ADDR
#define UART_DM_RX_TOTAL_SNAP_ADDR
Definition msm8974.c:46
UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK
#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK
Definition msm8974.c:105
UART_DM_GENERAL_CMD
#define UART_DM_GENERAL_CMD(a, v)
Definition msm8974.c:233
util.Read
Read(Tokens)
Definition util.py:6

◆ MSM8974InitializePort()

BOOLEAN MSM8974InitializePort ( _In_opt_ _Null_terminated_ PCHAR LoadOptions,
_Inout_ PCPPORT Port,
BOOLEAN MemoryMapped,
UCHAR AccessSize,
UCHAR BitWidth )
280{
281 UNREFERENCED_PARAMETER(LoadOptions);
282 UNREFERENCED_PARAMETER(AccessSize);
283
284 if (MemoryMapped == FALSE)
285 {
286 return FALSE;
287 }
288
289 if (BitWidth != 32)
290 {
291 return FALSE;
292 }
293
294 Port->Flags = 0;
295
296 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_DIS_RX);
297 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_DIS_TX);
298 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_ERR);
299 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_RX);
300 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_TX);
301 UART_DM_WRITE_REG(Port->Address, UART_DM_MR1_ADDR, UART_DM_MR1_DEFAULT);
302 UART_DM_WRITE_REG(Port->Address, UART_DM_MR2_ADDR, UART_DM_MR2_DEFAULT);
303
304 MSM8974SetBaud(Port, Port->BaudRate);
305
306 UART_DM_WRITE_REG(Port->Address, UART_DM_IMR_ADDR, UART_DM_IMR_DEFAULT);
307 UART_DM_WRITE_REG(Port->Address, UART_DM_IPR_ADDR, UART_DM_IPR_DEFAULT);
308 UART_DM_WRITE_REG(Port->Address, UART_DM_BADR_ADDR, UART_DM_BADR_DEFAULT);
309 UART_DM_WRITE_REG(Port->Address, UART_DM_DMEN_ADDR, 0);
310 UART_DM_WRITE_REG(Port->Address, UART_DM_DMRX_ADDR, UART_RX_BYTES_TO_RECEIVE);
311 UART_DM_CH_CMD(Port->Address, UART_DM_CH_CMD_RESET_STALE_IRQ);
312 UART_DM_GENERAL_CMD(Port->Address, UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT);
313 UART_DM_WRITE_REG(Port->Address,
314 UART_DM_CR_ADDR,
315 (UART_DM_CR_ENA_RX | UART_DM_CR_ENA_TX));
316
317 return TRUE;
318}
TRUE
#define TRUE
Definition BasicTypes.h:55
FALSE
#define FALSE
Definition BasicTypes.h:54
UART_DM_CR_RESET_ERR
#define UART_DM_CR_RESET_ERR
Definition msm8974.c:124
UART_DM_IPR_DEFAULT
#define UART_DM_IPR_DEFAULT
Definition msm8974.c:171
UART_DM_MR2_DEFAULT
#define UART_DM_MR2_DEFAULT
Definition msm8974.c:162
MSM8974SetBaud
BOOLEAN MSM8974SetBaud(_Inout_ PCPPORT Port, ULONG Rate)
Definition msm8974.c:321
UART_DM_MR2_ADDR
#define UART_DM_MR2_ADDR
Definition msm8974.c:29
UART_DM_IMR_ADDR
#define UART_DM_IMR_ADDR
Definition msm8974.c:44
UART_DM_CR_DIS_RX
#define UART_DM_CR_DIS_RX
Definition msm8974.c:118
UART_DM_CR_RESET_RX
#define UART_DM_CR_RESET_RX
Definition msm8974.c:122
UART_DM_CR_ENA_RX
#define UART_DM_CR_ENA_RX
Definition msm8974.c:117
UART_DM_CR_DIS_TX
#define UART_DM_CR_DIS_TX
Definition msm8974.c:120
UART_DM_DMEN_ADDR
#define UART_DM_DMEN_ADDR
Definition msm8974.c:36
UART_DM_BADR_DEFAULT
#define UART_DM_BADR_DEFAULT
Definition msm8974.c:177
UART_DM_CR_ENA_TX
#define UART_DM_CR_ENA_TX
Definition msm8974.c:119
UART_DM_MR1_ADDR
#define UART_DM_MR1_ADDR
Definition msm8974.c:28
UART_DM_IMR_DEFAULT
#define UART_DM_IMR_DEFAULT
Definition msm8974.c:165
UART_DM_BADR_ADDR
#define UART_DM_BADR_ADDR
Definition msm8974.c:38
UART_DM_MR1_DEFAULT
#define UART_DM_MR1_DEFAULT
Definition msm8974.c:161
UART_DM_CR_RESET_TX
#define UART_DM_CR_RESET_TX
Definition msm8974.c:123
UART_DM_IPR_ADDR
#define UART_DM_IPR_ADDR
Definition msm8974.c:30

◆ MSM8974PutByte()

UART_STATUS MSM8974PutByte ( _Inout_ PCPPORT Port,
UCHAR Byte,
BOOLEAN BusyWait )
567{
568 PUCHAR Address;
569
570 if ((Port == NULL) || (Port->Address == NULL))
571 {
572 return UartNotReady;
573 }
574
575 Address = Port->Address;
576
577 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
578 UART_DM_SR_TXEMT_BMSK) == 0)
579 {
580 if (BusyWait != FALSE)
581 {
582 while ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
583 UART_DM_ISR_TX_READY_BMSK) == 0)
584 ;
585 }
586 else if ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
587 UART_DM_ISR_TX_READY_BMSK) == 0)
588 {
589 return UartNotReady;
590 }
591 }
592
593 UART_DM_WRITE_REG(Address, UART_DM_NO_CHARS_FOR_TX_ADDR, 1);
594 UART_DM_GENERAL_CMD(Address, UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ);
595 UART_DM_WRITE_REG(Address, UART_DM_TF_ADDR, (UINT32)Byte);
596 return UartSuccess;
597}
UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ
#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ
Definition msm8974.c:216
UART_DM_NO_CHARS_FOR_TX_ADDR
#define UART_DM_NO_CHARS_FOR_TX_ADDR
Definition msm8974.c:37
UART_DM_SR_TXEMT_BMSK
#define UART_DM_SR_TXEMT_BMSK
Definition msm8974.c:86
UART_DM_ISR_TX_READY_BMSK
#define UART_DM_ISR_TX_READY_BMSK
Definition msm8974.c:99
UART_DM_TF_ADDR
#define UART_DM_TF_ADDR
Definition msm8974.c:47

◆ MSM8974RxReady()

BOOLEAN MSM8974RxReady ( _Inout_ PCPPORT Port)
619{
620 UINT32 Sr;
621
622 if ((Port == NULL) || (Port->Address == NULL))
623 {
624 return FALSE;
625 }
626
627 Sr = UART_DM_READ_REG(Port->Address, UART_DM_SR_ADDR);
628 if (CHECK_FLAG(Sr, UART_DM_SR_RXRDY_BMSK))
629 {
630 return TRUE;
631 }
632
633 return FALSE;
634}
CHECK_FLAG
#define CHECK_FLAG(_x, _f)
Definition uartp.h:27

◆ MSM8974SetBaud()

BOOLEAN MSM8974SetBaud ( _Inout_ PCPPORT Port,
ULONG Rate )
343{
344 UINT32 DivisorLatch;
345
346 if ((Port == NULL) || (Port->Address == NULL))
347 {
348 return FALSE;
349 }
350
351 //
352 // Clock rate is 1843200.
353 //
354
355 switch (Rate)
356 {
357 case 75:
358 DivisorLatch = 0x00;
359 break;
360 case 150:
361 DivisorLatch = 0x11;
362 break;
363 case 300:
364 DivisorLatch = 0x22;
365 break;
366 case 600:
367 DivisorLatch = 0x33;
368 break;
369 case 1200:
370 DivisorLatch = 0x44;
371 break;
372 case 2400:
373 DivisorLatch = 0x55;
374 break;
375 case 3600:
376 DivisorLatch = 0x66;
377 break;
378 case 4800:
379 DivisorLatch = 0x77;
380 break;
381 case 7200:
382 DivisorLatch = 0x88;
383 break;
384 case 9600:
385 DivisorLatch = 0x99;
386 break;
387 case 14400:
388 DivisorLatch = 0xAA;
389 break;
390 case 19200:
391 DivisorLatch = 0xBB;
392 break;
393 case 28800:
394 DivisorLatch = 0xCC;
395 break;
396 case 38400:
397 DivisorLatch = 0xDD;
398 break;
399 case 57600:
400 DivisorLatch = 0xEE;
401 break;
402 case 115200:
403 DivisorLatch = 0xFF;
404 break;
405 default:
406 DivisorLatch = 0xFF;
407 break;
408 }
409
410 UART_DM_WRITE_REG(Port->Address, UART_DM_CSR_ADDR, DivisorLatch);
411 Port->BaudRate = Rate;
412 return TRUE;
413}
UART_DM_CSR_ADDR
#define UART_DM_CSR_ADDR
Definition msm8974.c:41

Variable Documentation

◆ MSM8974HardwareDriver

UART_HARDWARE_DRIVER MSM8974HardwareDriver
Initial value:
= {
MSM8974InitializePort,
MSM8974SetBaud,
MSM8974GetByte,
MSM8974PutByte,
MSM8974RxReady}
MSM8974RxReady
BOOLEAN MSM8974RxReady(_Inout_ PCPPORT Port)
Definition msm8974.c:600
MSM8974GetByte
UART_STATUS MSM8974GetByte(_Inout_ PCPPORT Port, _Out_ PUCHAR Byte)
Definition msm8974.c:416
MSM8974PutByte
UART_STATUS MSM8974PutByte(_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait)
Definition msm8974.c:541
MSM8974InitializePort
BOOLEAN MSM8974InitializePort(_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
Definition msm8974.c:246
638 {
639 MSM8974InitializePort,
640 MSM8974SetBaud,
641 MSM8974GetByte,
642 MSM8974PutByte,
643 MSM8974RxReady};