HyperDbg Debugger
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Classes | |
struct | _MX6_UART_REGISTERS |
Macros | |
#define | MX6_UCR1_UARTEN (1 << 0) |
#define | MX6_UCR2_TXEN (1 << 2) |
#define | MX6_UCR2_RXEN (1 << 1) |
#define | MX6_UCR2_PREN (1 << 8) |
#define | MX6_UCR2_STPB (1 << 6) |
#define | MX6_UCR2_WRDSZ (1 << 5) |
#define | MX6_USR1_TRDY (1 << 13) |
#define | MX6_USR2_RDR (1 << 0) |
#define | MX6_RXD_CHARRDY (1 << 15) |
#define | MX6_RXD_ERR (1 << 14) |
#define | MX6_RXD_FRMERR (1 << 12) |
#define | MX6_RXD_PARERR (1 << 10) |
#define | MX6_RXD_DATA_MASK 0xFF |
#define | MX6_UFCR_TXTL_SHIFT 10 |
#define | MX6_UFCR_TXTL_MAX 32 |
#define | MX6_UFCR_TXTL_MASK 0x3F |
#define | MX6_USR1_PRTERRY_MASK (1 << 15) |
#define | MX6_USR1_ESCF_MASK (1 << 11) |
#define | MX6_USR1_FRMER_MASK (1 << 10) |
#define | MX6_USR1_AGTIM_MASK (1 << 8) |
#define | MX6_USR1_DTRD_MASK (1 << 7) |
#define | MX6_USR1_AIRINT_MASK (1 << 5) |
#define | MX6_USR1_AWAKE_MASK (1 << 4) |
#define | MX6_USR2_RDRDY_MASK 1 |
#define | MX6_UTS_RXEMPTY_MASK (1 << 5) |
Typedefs | |
typedef struct _MX6_UART_REGISTERS | MX6_UART_REGISTERS |
typedef struct _MX6_UART_REGISTERS * | PMX6_UART_REGISTERS |
Functions | |
C_ASSERT (FIELD_OFFSET(MX6_UART_REGISTERS, Umcr)==0xB8) | |
BOOLEAN | MX6InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth) |
BOOLEAN | MX6SetBaud (_Inout_ PCPPORT Port, ULONG Rate) |
UART_STATUS | MX6GetByte (_Inout_ PCPPORT Port, _Out_ PUCHAR Byte) |
UART_STATUS | MX6PutByte (_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait) |
BOOLEAN | MX6RxReady (_Inout_ PCPPORT Port) |
Variables | |
UART_HARDWARE_DRIVER | MX6HardwareDriver |
#define MX6_RXD_CHARRDY (1 << 15) |
#define MX6_RXD_DATA_MASK 0xFF |
#define MX6_RXD_ERR (1 << 14) |
#define MX6_RXD_FRMERR (1 << 12) |
#define MX6_RXD_PARERR (1 << 10) |
#define MX6_UCR1_UARTEN (1 << 0) |
#define MX6_UCR2_PREN (1 << 8) |
#define MX6_UCR2_RXEN (1 << 1) |
#define MX6_UCR2_STPB (1 << 6) |
#define MX6_UCR2_TXEN (1 << 2) |
#define MX6_UCR2_WRDSZ (1 << 5) |
#define MX6_UFCR_TXTL_MASK 0x3F |
#define MX6_UFCR_TXTL_MAX 32 |
#define MX6_UFCR_TXTL_SHIFT 10 |
#define MX6_USR1_AGTIM_MASK (1 << 8) |
#define MX6_USR1_AIRINT_MASK (1 << 5) |
#define MX6_USR1_AWAKE_MASK (1 << 4) |
#define MX6_USR1_DTRD_MASK (1 << 7) |
#define MX6_USR1_ESCF_MASK (1 << 11) |
#define MX6_USR1_FRMER_MASK (1 << 10) |
#define MX6_USR1_PRTERRY_MASK (1 << 15) |
#define MX6_USR1_TRDY (1 << 13) |
#define MX6_USR2_RDR (1 << 0) |
#define MX6_USR2_RDRDY_MASK 1 |
#define MX6_UTS_RXEMPTY_MASK (1 << 5) |
typedef struct _MX6_UART_REGISTERS MX6_UART_REGISTERS |
typedef struct _MX6_UART_REGISTERS * PMX6_UART_REGISTERS |
C_ASSERT | ( | FIELD_OFFSET(MX6_UART_REGISTERS, Umcr) | = =0xB8 | ) |
UART_STATUS MX6GetByte | ( | _Inout_ PCPPORT | Port, |
_Out_ PUCHAR | Byte ) |
BOOLEAN MX6InitializePort | ( | _In_opt_ _Null_terminated_ PCHAR | LoadOptions, |
_Inout_ PCPPORT | Port, | ||
BOOLEAN | MemoryMapped, | ||
UCHAR | AccessSize, | ||
UCHAR | BitWidth ) |
BOOLEAN MX6RxReady | ( | _Inout_ PCPPORT | Port | ) |
UART_HARDWARE_DRIVER MX6HardwareDriver |