Variables
str	MODELSIM = "/home/sina/intelFPGA/20.1/modelsim_ase/bin"

str	MODELSIM_VCD2WLF = MODELSIM + "/vcd2wlf"

str	MODELSIM_VSIM = MODELSIM + "/vsim"

str	CONFIG_TEST_MODULE_CLASS = ""

bool	CONFIG_SHOW_ALL_WAVES = True

list	CONFIG_WAVES_LIST = []

	current_script_path = os.path.dirname(os.path.abspath(__file__))

str	WAVE_OUTPUT_FILES_PATH

str	CONFIG_FILE_PATH = current_script_path + "/modelsim.config"

	result

	files = glob.glob(WAVE_OUTPUT_FILES_PATH + "/*")

	key

	latest_vcd_file = files[-1]

Variable Documentation

◆ CONFIG_FILE_PATH

str modelsim.CONFIG_FILE_PATH = current_script_path + "/modelsim.config"

bool modelsim.CONFIG_SHOW_ALL_WAVES = True

modelsim.CONFIG_TEST_MODULE_CLASS = ""

list modelsim.CONFIG_WAVES_LIST = []

modelsim.current_script_path = os.path.dirname(os.path.abspath(__file__))

modelsim.files = glob.glob(WAVE_OUTPUT_FILES_PATH + "/*")

modelsim.key

modelsim.latest_vcd_file = files[-1]

str modelsim.MODELSIM = "/home/sina/intelFPGA/20.1/modelsim_ase/bin"

str modelsim.MODELSIM_VCD2WLF = MODELSIM + "/vcd2wlf"

str modelsim.MODELSIM_VSIM = MODELSIM + "/vsim"

modelsim.result

Initial value:

1= subprocess.run(

2 ["sbt", "testOnly " + CONFIG_TEST_MODULE_CLASS + " -- -DwriteVcd=1"], stdout=subprocess.PIPE)

str modelsim.WAVE_OUTPUT_FILES_PATH

Initial value:

1= current_script_path + \

2 "/../test_run_dir/DUT_should_pass/"