pl011.c File Reference

#include "common.h"

Macros
#define	UART_DR   0x00
#define	UART_RSR   0x04
#define	UART_ECR   0x04
#define	UART_FR   0x18
#define	UART_ILPR   0x20
#define	UART_IBRD   0x24
#define	UART_FBRD   0x28
#define	UART_LCRH   0x2C
#define	UART_CR   0x30
#define	UART_IFLS   0x34
#define	UART_IMSC   0x38
#define	UART_RIS   0x3C
#define	UART_MIS   0x40
#define	UART_ICR   0x44
#define	UART_DMACR   0x48
#define	TOTAL_UART_REGISTER_SIZE   0x4C
#define	UART_FR_TXFE   0x80
#define	UART_FR_RXFF   0x40
#define	UART_FR_TXFF   0x20
#define	UART_FR_RXFE   0x10
#define	UART_FR_BUSY   0x08
#define	UART_LCRH_SPS   0x80
#define	UART_LCRH_WLEN_8   0x60
#define	UART_LCRH_WLEN_7   0x40
#define	UART_LCRH_WLEN_6   0x20
#define	UART_LCRH_WLEN_5   0x00
#define	UART_LCRH_FEN   0x10
#define	UART_LCRH_STP2   0x08
#define	UART_LCRH_EPS   0x04
#define	UART_LCRH_PEN   0x02
#define	UART_LCRH_BRK   0x01
#define	UART_CR_CTSEn   0x8000
#define	UART_CR_RTSEn   0x4000
#define	UART_CR_OUT2   0x2000
#define	UART_CR_OUT1   0x1000
#define	UART_CR_RTS   0x0800
#define	UART_CR_DTR   0x0400
#define	UART_CR_RXE   0x0200
#define	UART_CR_TXE   0x0100
#define	UART_CR_LBE   0x0080
#define	UART_CR_SIRLP   0x0004
#define	UART_CR_SIREN   0x0002
#define	UART_CR_UARTEN   0x0001
#define	UART_DR_OE   0x800
#define	UART_DR_BE   0x400
#define	UART_DR_PE   0x200
#define	UART_DR_FE   0x100
#define	PL011_READ_REGISTER_UCHAR(a, f)    (UCHAR)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_UCHAR(a))
#define	PL011_READ_REGISTER_USHORT(a, f)    (USHORT)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_USHORT(a))
#define	PL011_WRITE_REGISTER_UCHAR(a, d, f)    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_UCHAR(a, d))
#define	PL011_WRITE_REGISTER_USHORT(a, d, f)    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_USHORT(a, d))

Functions
BOOLEAN	PL011InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
BOOLEAN	SBSAInitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
BOOLEAN	SBSA32InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
BOOLEAN	PL011SetBaud (_Inout_ PCPPORT Port, ULONG Rate)
UART_STATUS	PL011GetByte (_Inout_ PCPPORT Port, _Out_ PUCHAR Byte)
UART_STATUS	PL011PutByte (_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait)
BOOLEAN	PL011RxReady (_Inout_ PCPPORT Port)

Variables
UART_HARDWARE_DRIVER	PL011HardwareDriver
UART_HARDWARE_DRIVER	SBSAHardwareDriver
UART_HARDWARE_DRIVER	SBSA32HardwareDriver

Macro Definition Documentation

PL011_READ_REGISTER_UCHAR

#define PL011_READ_REGISTER_UCHAR	(		a,
			f )    (UCHAR)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_UCHAR(a))

#define PL011_READ_REGISTER_UCHAR(a, f) \
    (UCHAR)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_UCHAR(a))

PL011_READ_REGISTER_USHORT

#define PL011_READ_REGISTER_USHORT	(		a,
			f )    (USHORT)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_USHORT(a))

#define PL011_READ_REGISTER_USHORT(a, f) \
    (USHORT)((f) ? READ_REGISTER_ULONG((PULONG)(a)) : READ_REGISTER_USHORT(a))

PL011_WRITE_REGISTER_UCHAR

#define PL011_WRITE_REGISTER_UCHAR	(		a,
			d,
			f )    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_UCHAR(a, d))

#define PL011_WRITE_REGISTER_UCHAR(a, d, f) \
    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_UCHAR(a, d))

PL011_WRITE_REGISTER_USHORT

#define PL011_WRITE_REGISTER_USHORT	(		a,
			d,
			f )    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_USHORT(a, d))

#define PL011_WRITE_REGISTER_USHORT(a, d, f) \
    ((f) ? WRITE_REGISTER_ULONG((PULONG)(a), d) : WRITE_REGISTER_USHORT(a, d))

TOTAL_UART_REGISTER_SIZE

#define TOTAL_UART_REGISTER_SIZE   0x4C

UART_CR

#define UART_CR   0x30

UART_CR_CTSEn

#define UART_CR_CTSEn   0x8000

UART_CR_DTR

#define UART_CR_DTR   0x0400

UART_CR_LBE

#define UART_CR_LBE   0x0080

UART_CR_OUT1

#define UART_CR_OUT1   0x1000

UART_CR_OUT2

#define UART_CR_OUT2   0x2000

UART_CR_RTS

#define UART_CR_RTS   0x0800

UART_CR_RTSEn

#define UART_CR_RTSEn   0x4000

UART_CR_RXE

#define UART_CR_RXE   0x0200

UART_CR_SIREN

#define UART_CR_SIREN   0x0002

UART_CR_SIRLP

#define UART_CR_SIRLP   0x0004

UART_CR_TXE

#define UART_CR_TXE   0x0100

UART_CR_UARTEN

#define UART_CR_UARTEN   0x0001

UART_DMACR

#define UART_DMACR   0x48

UART_DR

#define UART_DR   0x00

UART_DR_BE

#define UART_DR_BE   0x400

UART_DR_FE

#define UART_DR_FE   0x100

UART_DR_OE

#define UART_DR_OE   0x800

UART_DR_PE

#define UART_DR_PE   0x200

UART_ECR

#define UART_ECR   0x04

UART_FBRD

#define UART_FBRD   0x28

UART_FR

#define UART_FR   0x18

UART_FR_BUSY

#define UART_FR_BUSY   0x08

UART_FR_RXFE

#define UART_FR_RXFE   0x10

UART_FR_RXFF

#define UART_FR_RXFF   0x40

UART_FR_TXFE

#define UART_FR_TXFE   0x80

UART_FR_TXFF

#define UART_FR_TXFF   0x20

UART_IBRD

#define UART_IBRD   0x24

UART_ICR

#define UART_ICR   0x44

UART_IFLS

#define UART_IFLS   0x34

UART_ILPR

#define UART_ILPR   0x20

UART_IMSC

#define UART_IMSC   0x38

UART_LCRH

#define UART_LCRH   0x2C

UART_LCRH_BRK

#define UART_LCRH_BRK   0x01

UART_LCRH_EPS

#define UART_LCRH_EPS   0x04

UART_LCRH_FEN

#define UART_LCRH_FEN   0x10

UART_LCRH_PEN

#define UART_LCRH_PEN   0x02

UART_LCRH_SPS

#define UART_LCRH_SPS   0x80

UART_LCRH_STP2

#define UART_LCRH_STP2   0x08

UART_LCRH_WLEN_5

#define UART_LCRH_WLEN_5   0x00

UART_LCRH_WLEN_6

#define UART_LCRH_WLEN_6   0x20

UART_LCRH_WLEN_7

#define UART_LCRH_WLEN_7   0x40

UART_LCRH_WLEN_8

#define UART_LCRH_WLEN_8   0x60

UART_MIS

#define UART_MIS   0x40

UART_RIS

#define UART_RIS   0x3C

UART_RSR

#define UART_RSR   0x04

Function Documentation

PL011GetByte()

UART_STATUS PL011GetByte	(	_Inout_ PCPPORT	Port,
		_Out_ PUCHAR	Byte )

{
    BOOLEAN Force32Bit;
    USHORT  Fsr;
    USHORT  Value;
 
    if ((Port == NULL) || (Port->Address == NULL))
    {
        return UartNotReady;
    }
 
    Force32Bit = ((Port->Flags & PORT_FORCE_32BIT_IO) != 0);
 
    //
    // Get FIFO status.
    //
 
    Fsr = PL011_READ_REGISTER_USHORT((PUSHORT)(Port->Address + UART_FR),
                                     Force32Bit);
 
    //
    // Is at least one character available?
    //
 
    if ((Fsr & UART_FR_RXFE) == 0)
    {
        //
        // Fetch the data byte and associated error information.
        //
 
        Value =
            PL011_READ_REGISTER_USHORT((PUSHORT)(Port->Address + UART_DR),
                                       Force32Bit);
 
        //
        // Check for errors. Deliberately don't treat overrun as an error.
        //
 
        if ((Value & (UART_DR_PE | UART_DR_FE | UART_DR_BE)) != 0)
        {
            *Byte = 0;
            return UartError;
        }
 
        *Byte = Value & (UCHAR)0xFF;
        return UartSuccess;
    }
 
    return UartNoData;
}

PL011InitializePort()

BOOLEAN PL011InitializePort	(	_In_opt_ _Null_terminated_ PCHAR	LoadOptions,
		_Inout_ PCPPORT	Port,
		BOOLEAN	MemoryMapped,
		UCHAR	AccessSize,
		UCHAR	BitWidth )

{
    UINT16  Cr;
    BOOLEAN Force32Bit;
    UINT16  Fsr;
 
    UNREFERENCED_PARAMETER(LoadOptions);
    UNREFERENCED_PARAMETER(AccessSize);
 
    if (MemoryMapped == FALSE)
    {
        return FALSE;
    }
 
    if (BitWidth == 32)
    {
        Port->Flags = PORT_FORCE_32BIT_IO;
        Force32Bit  = TRUE;
    }
    else
    {
        Port->Flags = 0;
        Force32Bit  = FALSE;
    }
 
    //
    // Disable UART.
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                0,
                                Force32Bit);
 
    //
    // Flush the FIFO by disabling the FIFO.
    // FIFO need to be flushed before re-enabling the UART.
    //
 
    do
    {
        PL011_WRITE_REGISTER_UCHAR((PUCHAR)(Port->Address + UART_LCRH), 0, FALSE);
        Fsr = PL011_READ_REGISTER_USHORT((PUSHORT)(Port->Address + UART_FR), FALSE);
 
    } while ((Fsr & (UART_FR_RXFE | UART_FR_TXFE)) != (UART_FR_RXFE | UART_FR_TXFE));
 
    //
    // Set word length to 8 bits, enable the FIFO, disable parity.
    //
 
    PL011_WRITE_REGISTER_UCHAR(Port->Address + UART_LCRH,
                               (UART_LCRH_WLEN_8 | UART_LCRH_FEN),
                               Force32Bit);
 
    //
    // Clear all interrupts
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_IMSC),
                                0x0000,
                                Force32Bit);
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_ICR),
                                0x07FF,
                                Force32Bit);
 
    //
    // Enable UART, Enable Transmit and Receive, Enable RTS.
    //
    // The RTS hardware flow control is required to ensure RX FIFO won't be
    // overflowed on simulator.
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                (UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE),
                                Force32Bit);
 
    Cr = PL011_READ_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                    Force32Bit);
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                (Cr | UART_CR_UARTEN),
                                Force32Bit);
 
    return TRUE;
}

PL011PutByte()

UART_STATUS PL011PutByte	(	_Inout_ PCPPORT	Port,
		UCHAR	Byte,
		BOOLEAN	BusyWait )

{
    BOOLEAN Force32Bit;
 
    if ((Port == NULL) || (Port->Address == NULL))
    {
        return UartNotReady;
    }
 
    Force32Bit = ((Port->Flags & PORT_FORCE_32BIT_IO) != 0);
 
    //
    // Wait for port to be free and FIFO not full.
    //
    // _ARM_WORKAROUND_ modem control is not supported
    //
 
    if (BusyWait != FALSE)
    {
        while (PL011_READ_REGISTER_USHORT(
                   (PUSHORT)(Port->Address + UART_FR),
                   Force32Bit) &
               (UART_FR_TXFF))
            ;
    }
    else
    {
        if (PL011_READ_REGISTER_USHORT(
                (PUSHORT)(Port->Address + UART_FR),
                Force32Bit) &
            (UART_FR_TXFF))
        {
            return UartNotReady;
        }
    }
 
    //
    // Send the byte.
    //
 
    PL011_WRITE_REGISTER_UCHAR(Port->Address + UART_DR, Byte, Force32Bit);
    return UartSuccess;
}

PL011RxReady()

BOOLEAN PL011RxReady

(

_Inout_ PCPPORT

Port

)

{
    PUCHAR  BaseAddress;
    USHORT  Flags;
    BOOLEAN Force32Bit;
 
    if ((Port == NULL) || (Port->Address == NULL))
    {
        return FALSE;
    }
 
    //
    // Read the Flag Register to determine if there is any pending
    // data to read.
    //
 
    BaseAddress = Port->Address;
    Force32Bit  = ((Port->Flags & PORT_FORCE_32BIT_IO) != 0);
    Flags       = PL011_READ_REGISTER_USHORT((PUSHORT)(BaseAddress + UART_FR),
                                       Force32Bit);
 
    //
    // Check the "receive FIFO empty" flag. If it is clear, then at least one
    // byte is available.
    //
 
    if (CHECK_FLAG(Flags, UART_FR_RXFE) == 0)
    {
        return TRUE;
    }
 
    return FALSE;
}

PL011SetBaud()

BOOLEAN PL011SetBaud	(	_Inout_ PCPPORT	Port,
		ULONG	Rate )

{
    if ((Port == NULL) || (Port->Address == NULL))
    {
        return FALSE;
    }
 
    //
    // Remember the baud rate.
    //
 
    Port->BaudRate = Rate;
    return TRUE;
}

SBSA32InitializePort()

BOOLEAN SBSA32InitializePort	(	_In_opt_ _Null_terminated_ PCHAR	LoadOptions,
		_Inout_ PCPPORT	Port,
		BOOLEAN	MemoryMapped,
		UCHAR	AccessSize,
		UCHAR	BitWidth )

{
    UNREFERENCED_PARAMETER(BitWidth);
 
    return SBSAInitializePort(LoadOptions, Port, MemoryMapped, AccessSize, 32);
}

SBSAInitializePort()

BOOLEAN SBSAInitializePort	(	_In_opt_ _Null_terminated_ PCHAR	LoadOptions,
		_Inout_ PCPPORT	Port,
		BOOLEAN	MemoryMapped,
		UCHAR	AccessSize,
		UCHAR	BitWidth )

{
    UINT16  Cr;
    BOOLEAN Force32Bit;
 
    UNREFERENCED_PARAMETER(LoadOptions);
    UNREFERENCED_PARAMETER(AccessSize);
 
    if (MemoryMapped == FALSE)
    {
        return FALSE;
    }
 
    if (BitWidth == 32)
    {
        Port->Flags = PORT_FORCE_32BIT_IO;
        Force32Bit  = TRUE;
    }
    else
    {
        Port->Flags = 0;
        Force32Bit  = FALSE;
    }
 
    //
    // Disable UART.
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                0,
                                Force32Bit);
 
    //
    // Set word length to 8 bits, enable the FIFO, disable parity.
    //
 
    PL011_WRITE_REGISTER_UCHAR(Port->Address + UART_LCRH,
                               (UART_LCRH_WLEN_8 | UART_LCRH_FEN),
                               Force32Bit);
 
    //
    // Clear all interrupts
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_IMSC),
                                0x0000,
                                Force32Bit);
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_ICR),
                                0x07FF,
                                Force32Bit);
 
    //
    // Enable UART, Enable Transmit and Receive, Enable RTS.
    //
    // The RTS hardware flow control is required to ensure RX FIFO won't be
    // overflowed on simulator.
    //
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                (UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE),
                                Force32Bit);
 
    Cr = PL011_READ_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                    Force32Bit);
 
    PL011_WRITE_REGISTER_USHORT((PUSHORT)(Port->Address + UART_CR),
                                (Cr | UART_CR_UARTEN),
                                Force32Bit);
 
    return TRUE;
}

Variable Documentation

PL011HardwareDriver

UART_HARDWARE_DRIVER PL011HardwareDriver

Initial value:

= {
    PL011InitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady}

                                           {
    PL011InitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady};

SBSA32HardwareDriver

UART_HARDWARE_DRIVER SBSA32HardwareDriver

Initial value:

= {
    SBSA32InitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady}

                                            {
    SBSA32InitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady};

SBSAHardwareDriver

UART_HARDWARE_DRIVER SBSAHardwareDriver

Initial value:

= {
    SBSAInitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady}

                                          {
    SBSAInitializePort,
    PL011SetBaud,
    PL011GetByte,
    PL011PutByte,
    PL011RxReady};