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HyperDbg Debugger
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#include "common.h"Classes | |
| struct | _DW_APB_SSI_REGISTERS |
| struct | _SERIAL_PORT_MAX311XE |
Typedefs | |
| typedef struct _DW_APB_SSI_REGISTERS | DW_APB_SSI_REGISTERS |
| typedef struct _DW_APB_SSI_REGISTERS * | PDW_APB_SSI_REGISTERS |
| typedef struct _SERIAL_PORT_MAX311XE | SERIAL_PORT_MAX311XE |
| typedef struct _SERIAL_PORT_MAX311XE * | PSERIAL_PORT_MAX311XE |
Functions | |
| BOOLEAN | SpiMax311SetBaud (_Inout_ PCPPORT Port, ULONG Rate) |
| VOID | SpiInit (_Inout_ PDW_APB_SSI_REGISTERS Spi, UINT16 ControlRegister0, UINT16 ControlRegister1, UINT16 BaudRateRegister) |
| UINT16 | SpiSend16 (_In_ PCPPORT Port, UINT16 Value) |
| VOID | SpiMax311BufferRxData (UINT16 Value) |
| BOOLEAN | SpiMax311TxEmpty (_In_ PCPPORT Port) |
| BOOLEAN | SpiMax311InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth) |
| UART_STATUS | SpiMax311GetByte (_Inout_ PCPPORT Port, _Out_ PUCHAR Byte) |
| UART_STATUS | SpiMax311PutByte (_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait) |
| BOOLEAN | SpiMax311RxReady (_In_ PCPPORT Port) |
Variables | |
| UART_HARDWARE_DRIVER | SpiMax311HardwareDriver |
| #define BAUDR_MAX_RATE 2 |
| #define BAUDR_OFF 0 |
| #define CRTLR0_SLV_OE (1 << 10) |
| #define CTRLR0_DFS 15 |
| #define CTRLR0_FRF_MOTOROLA_SPI 0 |
| #define CTRLR0_FRF_NATIONAL_SEMICONDUCTORS_MICROWIRE (2 << 4) |
| #define CTRLR0_FRF_TEXAS_INSTRUMENTS_SSP (1 << 4) |
| #define CTRLR0_SCPH (1 << 6) |
| #define CTRLR0_SCPOL (1 << 7) |
| #define CTRLR0_TMOD_EEPROM (3 << 8) |
| #define CTRLR0_TMOD_RX (2 << 8) |
| #define CTRLR0_TMOD_TX (1 << 8) |
| #define CTRLR0_TMOD_TX_RX 0 |
| #define MAX311XE_RC_DIV_1 0 |
| #define MAX311XE_RC_DIV_12 10 |
| #define MAX311XE_RC_DIV_128 7 |
| #define MAX311XE_RC_DIV_16 4 |
| #define MAX311XE_RC_DIV_192 14 |
| #define MAX311XE_RC_DIV_2 1 |
| #define MAX311XE_RC_DIV_24 11 |
| #define MAX311XE_RC_DIV_3 8 |
| #define MAX311XE_RC_DIV_32 5 |
| #define MAX311XE_RC_DIV_384 15 |
| #define MAX311XE_RC_DIV_4 2 |
| #define MAX311XE_RC_DIV_48 12 |
| #define MAX311XE_RC_DIV_6 9 |
| #define MAX311XE_RC_DIV_64 6 |
| #define MAX311XE_RC_DIV_8 3 |
| #define MAX311XE_RC_DIV_96 13 |
| #define MAX311XE_RC_FEN_BAR (1 << 13) |
| #define MAX311XE_RC_IRDA (1 << 7) |
| #define MAX311XE_RC_L (1 << 4) |
| #define MAX311XE_RC_PE (1 << 5) |
| #define MAX311XE_RC_PM_BAR (1 << 9) |
| #define MAX311XE_RC_R (1 << 15) |
| #define MAX311XE_RC_RAM_BAR (1 << 8) |
| #define MAX311XE_RC_RM_BAR (1 << 10) |
| #define MAX311XE_RC_SHDNI (1 << 12) |
| #define MAX311XE_RC_ST (1 << 6) |
| #define MAX311XE_RC_T (1 << 14) |
| #define MAX311XE_RC_TM_BAR (1 << 11) |
| #define MAX311XE_RD_CTS (1 << 9) |
| #define MAX311XE_RD_DATA 0xFF |
| #define MAX311XE_RD_PR (1 << 8) |
| #define MAX311XE_RD_R (1 << 15) |
| #define MAX311XE_RD_RA_FE (1 << 10) |
| #define MAX311XE_RD_T (1 << 14) |
| #define MAX311XE_READ_CONFIG (1 << 14) |
| #define MAX311XE_READ_DATA 0 |
| #define MAX311XE_WC_DIV_1 0 |
| #define MAX311XE_WC_DIV_12 10 |
| #define MAX311XE_WC_DIV_128 7 |
| #define MAX311XE_WC_DIV_16 4 |
| #define MAX311XE_WC_DIV_192 14 |
| #define MAX311XE_WC_DIV_2 1 |
| #define MAX311XE_WC_DIV_24 11 |
| #define MAX311XE_WC_DIV_3 8 |
| #define MAX311XE_WC_DIV_32 5 |
| #define MAX311XE_WC_DIV_384 15 |
| #define MAX311XE_WC_DIV_4 2 |
| #define MAX311XE_WC_DIV_48 12 |
| #define MAX311XE_WC_DIV_6 9 |
| #define MAX311XE_WC_DIV_64 6 |
| #define MAX311XE_WC_DIV_8 3 |
| #define MAX311XE_WC_DIV_96 13 |
| #define MAX311XE_WC_FEN_BAR (1 << 13) |
| #define MAX311XE_WC_IRDA (1 << 7) |
| #define MAX311XE_WC_L (1 << 4) |
| #define MAX311XE_WC_PE (1 << 5) |
| #define MAX311XE_WC_PM_BAR (1 << 9) |
| #define MAX311XE_WC_RAM_BAR (1 << 8) |
| #define MAX311XE_WC_RM_BAR (1 << 10) |
| #define MAX311XE_WC_SHDNI (1 << 12) |
| #define MAX311XE_WC_ST (1 << 6) |
| #define MAX311XE_WC_TM_BAR (1 << 11) |
| #define MAX311XE_WD_DATA 0xFF |
| #define MAX311XE_WD_PT (1 << 8) |
| #define MAX311XE_WD_RTS_BAR (1 << 9) |
| #define MAX311XE_WD_TE_BAR (1 << 10) |
| #define MAX311XE_WRITE_CONFIG (3 << 14) |
| #define MAX311XE_WRITE_DATA (2 << 14) |
| #define RECEIVE_BUFFER_SIZE 1024 |
| #define SELECTOR_2MB_FLASH 4 |
| #define SELECTOR_LED 1 |
| #define SELECTOR_UART 2 |
| #define SR_BUSY (1 << 0) |
| #define SR_DCOL (1 << 6) |
| #define SR_RFF (1 << 4) |
| #define SR_RFNE (1 << 3) |
| #define SR_TFE (1 << 2) |
| #define SR_TFNF (1 << 1) |
| #define SR_TXE (1 << 5) |
| #define SSIENR_SSI_EN 1 |
| typedef struct _DW_APB_SSI_REGISTERS DW_APB_SSI_REGISTERS |
| typedef struct _DW_APB_SSI_REGISTERS * PDW_APB_SSI_REGISTERS |
| typedef struct _SERIAL_PORT_MAX311XE * PSERIAL_PORT_MAX311XE |
| typedef struct _SERIAL_PORT_MAX311XE SERIAL_PORT_MAX311XE |
| VOID SpiInit | ( | _Inout_ PDW_APB_SSI_REGISTERS | Spi, |
| UINT16 | ControlRegister0, | ||
| UINT16 | ControlRegister1, | ||
| UINT16 | BaudRateRegister ) |
| UART_STATUS SpiMax311GetByte | ( | _Inout_ PCPPORT | Port, |
| _Out_ PUCHAR | Byte ) |
| BOOLEAN SpiMax311InitializePort | ( | _In_opt_ _Null_terminated_ PCHAR | LoadOptions, |
| _Inout_ PCPPORT | Port, | ||
| BOOLEAN | MemoryMapped, | ||
| UCHAR | AccessSize, | ||
| UCHAR | BitWidth ) |
| BOOLEAN SpiMax311RxReady | ( | _In_ PCPPORT | Port | ) |
| BOOLEAN SpiMax311TxEmpty | ( | _In_ PCPPORT | Port | ) |
| UART_HARDWARE_DRIVER SpiMax311HardwareDriver |