MSR_LBR_INFO Union Reference

#include <LbrDefinitions.h>

Public Attributes
struct {
UINT64   CycleCount: 16
UINT64   Reserved: 40
UINT64   BrType_OnlyArchLbr: 4
UINT64   CycCntValid_OnlyArchLbr: 1
UINT64   TsxAbort: 1
UINT64   InTsx: 1
UINT64   Mispred: 1
};
UINT64	AsUInt
struct {
UINT64   CycleCount: 16
UINT64   Reserved: 40
UINT64   BrType_OnlyArchLbr: 4
UINT64   CycCntValid_OnlyArchLbr: 1
UINT64   TsxAbort: 1
UINT64   InTsx: 1
UINT64   Mispred: 1
};

Detailed Description

MSR_LBR_INFO_x - Last Branch Record Info Register Register Address: 1200H-121FH, 4608-4639

Member Data Documentation

[struct]

struct { ... } MSR_LBR_INFO

[struct]

struct { ... } MSR_LBR_INFO

AsUInt

UINT64 MSR_LBR_INFO::AsUInt

BrType_OnlyArchLbr

UINT64 MSR_LBR_INFO::BrType_OnlyArchLbr

Bits 59:56 - Branch type recorded by this LBR entry. Encodings: 0000b = COND 0001b = JMP Indirect 0010b = JMP Direct 0011b = CALL Indirect 0100b = CALL Direct 0101b = RET 011xb = Reserved 1xxxb = Other Branch

CycCntValid_OnlyArchLbr

UINT64 MSR_LBR_INFO::CycCntValid_OnlyArchLbr

Bit 60 - When set, the CycleCount field contains a valid elapsed cycle count

CycleCount

UINT64 MSR_LBR_INFO::CycleCount

Bits 15:0 - Elapsed core clocks since last update to the LBR stack (saturating)

InTsx

UINT64 MSR_LBR_INFO::InTsx

Bit 62 - When set, indicates the branch retired during a TSX transaction. Undefined on processors that do not support Intel TSX (CPUID.07H.00H:EBX.HLE[4] = 0 and CPUID.07H.00H:EBX.RTM[11] = 0).

Mispred

UINT64 MSR_LBR_INFO::Mispred

Bit 63 - Branch misprediction flag. When set, the target of the branch was mispredicted and/or the direction (taken/non-taken) was mispredicted. When clear, the branch target/direction was correctly predicted.

Reserved

UINT64 MSR_LBR_INFO::Reserved

Bits 55:16 - Undefined. May be zero or non-zero. Writes of non-zero values do not fault, but reads may return a different value.

TsxAbort

UINT64 MSR_LBR_INFO::TsxAbort

Bit 61 - TSX Abort indicator. When set: LBR_FROM = EIP at the time of the TSX Abort LBR_TO = EIP of the start of HLE region OR EIP of the RTM Abort Handler Undefined on processors that do not support Intel TSX (CPUID.07H.00H:EBX.HLE[4] = 0 and CPUID.07H.00H:EBX.RTM[11] = 0).

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The documentation for this union was generated from the following files:

• hyperdbg/build/bin/debug/SDK/headers/LbrDefinitions.h
• hyperdbg/include/SDK/headers/LbrDefinitions.h