HyperDbg Debugger
|
Namespaces | |
namespace | modelsim |
Variables | |
str | modelsim.MODELSIM = "/home/sina/intelFPGA/20.1/modelsim_ase/bin" |
str | modelsim.MODELSIM_VCD2WLF = MODELSIM + "/vcd2wlf" |
str | modelsim.MODELSIM_VSIM = MODELSIM + "/vsim" |
str | modelsim.CONFIG_TEST_MODULE_CLASS = "" |
bool | modelsim.CONFIG_SHOW_ALL_WAVES = True |
list | modelsim.CONFIG_WAVES_LIST = [] |
modelsim.current_script_path = os.path.dirname(os.path.abspath(__file__)) | |
str | modelsim.WAVE_OUTPUT_FILES_PATH |
str | modelsim.CONFIG_FILE_PATH = current_script_path + "/modelsim.config" |
modelsim.result | |
modelsim.files = glob.glob(WAVE_OUTPUT_FILES_PATH + "/*") | |
modelsim.key | |
modelsim.latest_vcd_file = files[-1] | |