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Macros | Functions | Variables
msm8x60.c File Reference
#include "common.h"

Macros

#define UART_RX_BYTES_TO_RECEIVE   0x2000
 
#define RX_FIFO_WIDTH   sizeof(UINT32)
 
#define UART_DM_MR1_ADDR   0x00000000
 
#define UART_DM_MR2_ADDR   0x00000004
 
#define UART_DM_SR_ADDR   0x00000008
 
#define UART_DM_CSR_ADDR   0x00000008
 
#define UART_DM_CR_ADDR   0x00000010
 
#define UART_DM_ISR_ADDR   0x00000014
 
#define UART_DM_IMR_ADDR   0x00000014
 
#define UART_DM_IPR_ADDR   0x00000018
 
#define UART_DM_TFWR_ADDR   0x0000001c
 
#define UART_DM_RFWR_ADDR   0x00000020
 
#define UART_DM_HCR_ADDR   0x00000024
 
#define UART_DM_DMRX_ADDR   0x00000034
 
#define UART_DM_IRDA_ADDR   0x00000038
 
#define UART_DM_RX_TOTAL_SNAP_ADDR   0x00000038
 
#define UART_DM_DMEN_ADDR   0x0000003c
 
#define UART_DM_NO_CHARS_FOR_TX_ADDR   0x00000040
 
#define UART_DM_BADR_ADDR   0x00000044
 
#define UART_DM_TXFS_ADDR   0x0000004c
 
#define UART_DM_RXFS_ADDR   0x00000050
 
#define UART_DM_TF_ADDR   0x00000070
 
#define UART_DM_RF_ADDR   0x00000070
 
#define UART_DM_SIM_CFG_ADDR   0x00000080
 
#define UART_DM_MR1_RFRC   0x80
 
#define UART_DM_MR1_CTSC   0x40
 
#define UART_DM_MR2_LOOPBACK   0x80
 
#define UART_DM_MR2_ERRMODE   0x40
 
#define UART_DM_MR2_5BPC   0x00
 
#define UART_DM_MR2_6BPC   0x10
 
#define UART_DM_MR2_7BPC   0x20
 
#define UART_DM_MR2_8BPC   0x30
 
#define UART_DM_MR2_05SB   0x00
 
#define UART_DM_MR2_1SB   0x04
 
#define UART_DM_MR2_15SB   0x08
 
#define UART_DM_MR2_2SB   0x0C
 
#define UART_DM_MR2_NOPAR   0x00
 
#define UART_DM_MR2_OPAR   0x01
 
#define UART_DM_MR2_EPAR   0x02
 
#define UART_DM_MR2_SPAR   0x03
 
#define UART_DM_SR_RXRDY_BMSK   0x1
 
#define UART_DM_SR_TXRDY_BMSK   0x4
 
#define UART_DM_SR_TXEMT_BMSK   0x8
 
#define UART_DM_SR_UART_OVERRUN_BMSK   0x10
 
#define UART_DM_SR_PAR_FRAME_ERR_BMSK   0x20
 
#define UART_DM_SR_RX_BREAK_BMSK   0x40
 
#define UART_DM_SR_HUNT_CHAR_BMSK   0x80
 
#define UART_DM_SR_ERROR_BMSK
 
#define UART_DM_ISR_RXSTALE_BMSK   0x8
 
#define UART_DM_ISR_TX_READY_BMSK   0x80
 
#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK   0x7f
 
#define UART_DM_DMA_EN_RXTX_DM_DIS   0x00
 
#define UART_DM_CR_ENA_RX   0x01
 
#define UART_DM_CR_DIS_RX   0x02
 
#define UART_DM_CR_ENA_TX   0x04
 
#define UART_DM_CR_DIS_TX   0x08
 
#define UART_DM_CR_NULL_CMD   0x0000
 
#define UART_DM_CR_RESET_RX   0x0010
 
#define UART_DM_CR_RESET_TX   0x0020
 
#define UART_DM_CR_RESET_ERR   0x0030
 
#define UART_DM_CR_RESET_BRK_INT   0x0040
 
#define UART_DM_CR_STA_BRK   0x0050
 
#define UART_DM_CR_STO_BRK   0x0060
 
#define UART_DM_CR_CLR_DCTS   0x0070
 
#define UART_DM_CR_RESET_STALE   0x0080
 
#define UART_DM_CR_SAMP_MODE   0x0090
 
#define UART_DM_CR_TEST_PARITY   0x00A0
 
#define UART_DM_CR_TEST_FRAME   0x00B0
 
#define UART_DM_CR_RESET_SAMPLE   0x00C0
 
#define UART_DM_CR_SET_RFR   0x00D0
 
#define UART_DM_CR_RESET_RFR   0x00E0
 
#define UART_DM_CR_RESET_TX_ERR   0x0800
 
#define UART_DM_CR_RESET_TX_DONE   0x0810
 
#define UART_DM_CR_ENA_CR_PROT   0x0100
 
#define UART_DM_CR_DIS_CR_PROT   0x0200
 
#define UART_DM_CR_RESET_TX_RDY   0x0300
 
#define UART_DM_CR_FORCE_STALE   0x0400
 
#define UART_DM_CR_ENA_STALE_EVT   0x0500
 
#define UART_DM_CR_DIS_STALE_EVT   0x0600
 
#define UART_DM_IMR_TX_DONE   0x200
 
#define UART_DM_IMR_TX_ERROR   0x100
 
#define UART_DM_IMR_TX_READY   0x080
 
#define UART_DM_IMR_CUR_CTS   0x040
 
#define UART_DM_IMR_DELTA_CTS   0x020
 
#define UART_DM_IMR_RXLEV   0x010
 
#define UART_DM_IMR_RXSTALE   0x008
 
#define UART_DM_IMR_RXBREAK   0x004
 
#define UART_DM_IMR_RXHUNT   0x002
 
#define UART_DM_IMR_TXLEV   0x001
 
#define UART_DM_IMR_NONE   0x000
 
#define UART_DM_MR1_DEFAULT   0
 
#define UART_DM_MR2_DEFAULT
 
#define UART_DM_IMR_DEFAULT   0
 
#define UART_DM_IPR_DEFAULT   0x2
 
#define UART_DM_BADR_DEFAULT   0x70
 
#define UART_DM_IRDA_DISABLE   0x00
 
#define UART_DM_CH_CMD_RESET_RECEIVER   0x01
 
#define UART_DM_CH_CMD_RESET_TRANSMITTER   0x02
 
#define UART_DM_CH_CMD_RESET_ERROR_STATUS   0x03
 
#define UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ   0x04
 
#define UART_DM_CH_CMD_START_BREAK   0x05
 
#define UART_DM_CH_CMD_STOP_BREAK   0x06
 
#define UART_DM_CH_CMD_RESET_CTS_N   0x07
 
#define UART_DM_CH_CMD_RESET_STALE_IRQ   0x08
 
#define UART_DM_CH_CMD_PACKET_MODE   0x09
 
#define UART_DM_CH_CMD_TEST_PARITY_ON   0x0A
 
#define UART_DM_CH_CMD_TEST_FRAME_ON   0x0B
 
#define UART_DM_CH_CMD_MODE_RESET   0x0C
 
#define UART_DM_CH_CMD_SET_RFR_N   0x0D
 
#define UART_DM_CH_CMD_RESET_RFR_N   0x0E
 
#define UART_DM_CH_CMD_UART_RESET_INT   0x0F
 
#define UART_DM_CH_CMD_RESET_TX_ERROR   0x10
 
#define UART_DM_CH_CMD_CLEAR_TX_DONE   0x11
 
#define UART_DM_CH_CMD_RESET_BRK_START_IRQ   0x12
 
#define UART_DM_CH_CMD_RESET_BRK_END_IRQ   0x13
 
#define UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ   0x14
 
#define UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE   0x01
 
#define UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE   0x02
 
#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ   0x03
 
#define UART_DM_GENERAL_CMD_SW_FORCE_STALE   0x04
 
#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT   0x05
 
#define UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT   0x06
 
#define UART_DM_READ_REG(addr, offset)    READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))
 
#define UART_DM_WRITE_REG(addr, offset, val)    WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)
 
#define UART_DM_CH_CMD(a, v)
 
#define UART_DM_GENERAL_CMD(a, v)    UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)
 

Functions

BOOLEAN MSM8x60SetBaud (_Inout_ PCPPORT Port, ULONG Rate)
 
BOOLEAN MSM8x60InitializePort (_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
 
UART_STATUS MSM8x60GetByte (_Inout_ PCPPORT Port, _Out_ PUCHAR Byte)
 
UART_STATUS MSM8x60PutByte (_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait)
 
BOOLEAN MSM8x60RxReady (_Inout_ PCPPORT Port)
 

Variables

UART_HARDWARE_DRIVER MSM8x60HardwareDriver
 

Macro Definition Documentation

◆ RX_FIFO_WIDTH

#define RX_FIFO_WIDTH   sizeof(UINT32)

◆ UART_DM_BADR_ADDR

#define UART_DM_BADR_ADDR   0x00000044

◆ UART_DM_BADR_DEFAULT

#define UART_DM_BADR_DEFAULT   0x70

◆ UART_DM_CH_CMD

#define UART_DM_CH_CMD ( a,
v )
Value:
UART_DM_WRITE_REG((a), \
UART_DM_CR_ADDR, \
((((v) >> 4) & 0x1) << 11) | (((v) & 0xF) << 4))
UART_DM_WRITE_REG
#define UART_DM_WRITE_REG(addr, offset, val)
Definition msm8x60.c:227
UART_DM_CR_ADDR
#define UART_DM_CR_ADDR
Definition msm8x60.c:32
230#define UART_DM_CH_CMD(a, v) \
231 UART_DM_WRITE_REG((a), \
232 UART_DM_CR_ADDR, \
233 ((((v) >> 4) & 0x1) << 11) | (((v) & 0xF) << 4))

◆ UART_DM_CH_CMD_CLEAR_TX_DONE

#define UART_DM_CH_CMD_CLEAR_TX_DONE   0x11

◆ UART_DM_CH_CMD_MODE_RESET

#define UART_DM_CH_CMD_MODE_RESET   0x0C

◆ UART_DM_CH_CMD_PACKET_MODE

#define UART_DM_CH_CMD_PACKET_MODE   0x09

◆ UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ

#define UART_DM_CH_CMD_RESET_BREAK_CHANGE_IRQ   0x04

◆ UART_DM_CH_CMD_RESET_BRK_END_IRQ

#define UART_DM_CH_CMD_RESET_BRK_END_IRQ   0x13

◆ UART_DM_CH_CMD_RESET_BRK_START_IRQ

#define UART_DM_CH_CMD_RESET_BRK_START_IRQ   0x12

◆ UART_DM_CH_CMD_RESET_CTS_N

#define UART_DM_CH_CMD_RESET_CTS_N   0x07

◆ UART_DM_CH_CMD_RESET_ERROR_STATUS

#define UART_DM_CH_CMD_RESET_ERROR_STATUS   0x03

◆ UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ

#define UART_DM_CH_CMD_RESET_PAR_FRAME_ERR_IRQ   0x14

◆ UART_DM_CH_CMD_RESET_RECEIVER

#define UART_DM_CH_CMD_RESET_RECEIVER   0x01

◆ UART_DM_CH_CMD_RESET_RFR_N

#define UART_DM_CH_CMD_RESET_RFR_N   0x0E

◆ UART_DM_CH_CMD_RESET_STALE_IRQ

#define UART_DM_CH_CMD_RESET_STALE_IRQ   0x08

◆ UART_DM_CH_CMD_RESET_TRANSMITTER

#define UART_DM_CH_CMD_RESET_TRANSMITTER   0x02

◆ UART_DM_CH_CMD_RESET_TX_ERROR

#define UART_DM_CH_CMD_RESET_TX_ERROR   0x10

◆ UART_DM_CH_CMD_SET_RFR_N

#define UART_DM_CH_CMD_SET_RFR_N   0x0D

◆ UART_DM_CH_CMD_START_BREAK

#define UART_DM_CH_CMD_START_BREAK   0x05

◆ UART_DM_CH_CMD_STOP_BREAK

#define UART_DM_CH_CMD_STOP_BREAK   0x06

◆ UART_DM_CH_CMD_TEST_FRAME_ON

#define UART_DM_CH_CMD_TEST_FRAME_ON   0x0B

◆ UART_DM_CH_CMD_TEST_PARITY_ON

#define UART_DM_CH_CMD_TEST_PARITY_ON   0x0A

◆ UART_DM_CH_CMD_UART_RESET_INT

#define UART_DM_CH_CMD_UART_RESET_INT   0x0F

◆ UART_DM_CR_ADDR

#define UART_DM_CR_ADDR   0x00000010

◆ UART_DM_CR_CLR_DCTS

#define UART_DM_CR_CLR_DCTS   0x0070

◆ UART_DM_CR_DIS_CR_PROT

#define UART_DM_CR_DIS_CR_PROT   0x0200

◆ UART_DM_CR_DIS_RX

#define UART_DM_CR_DIS_RX   0x02

◆ UART_DM_CR_DIS_STALE_EVT

#define UART_DM_CR_DIS_STALE_EVT   0x0600

◆ UART_DM_CR_DIS_TX

#define UART_DM_CR_DIS_TX   0x08

◆ UART_DM_CR_ENA_CR_PROT

#define UART_DM_CR_ENA_CR_PROT   0x0100

◆ UART_DM_CR_ENA_RX

#define UART_DM_CR_ENA_RX   0x01

◆ UART_DM_CR_ENA_STALE_EVT

#define UART_DM_CR_ENA_STALE_EVT   0x0500

◆ UART_DM_CR_ENA_TX

#define UART_DM_CR_ENA_TX   0x04

◆ UART_DM_CR_FORCE_STALE

#define UART_DM_CR_FORCE_STALE   0x0400

◆ UART_DM_CR_NULL_CMD

#define UART_DM_CR_NULL_CMD   0x0000

◆ UART_DM_CR_RESET_BRK_INT

#define UART_DM_CR_RESET_BRK_INT   0x0040

◆ UART_DM_CR_RESET_ERR

#define UART_DM_CR_RESET_ERR   0x0030

◆ UART_DM_CR_RESET_RFR

#define UART_DM_CR_RESET_RFR   0x00E0

◆ UART_DM_CR_RESET_RX

#define UART_DM_CR_RESET_RX   0x0010

◆ UART_DM_CR_RESET_SAMPLE

#define UART_DM_CR_RESET_SAMPLE   0x00C0

◆ UART_DM_CR_RESET_STALE

#define UART_DM_CR_RESET_STALE   0x0080

◆ UART_DM_CR_RESET_TX

#define UART_DM_CR_RESET_TX   0x0020

◆ UART_DM_CR_RESET_TX_DONE

#define UART_DM_CR_RESET_TX_DONE   0x0810

◆ UART_DM_CR_RESET_TX_ERR

#define UART_DM_CR_RESET_TX_ERR   0x0800

◆ UART_DM_CR_RESET_TX_RDY

#define UART_DM_CR_RESET_TX_RDY   0x0300

◆ UART_DM_CR_SAMP_MODE

#define UART_DM_CR_SAMP_MODE   0x0090

◆ UART_DM_CR_SET_RFR

#define UART_DM_CR_SET_RFR   0x00D0

◆ UART_DM_CR_STA_BRK

#define UART_DM_CR_STA_BRK   0x0050

◆ UART_DM_CR_STO_BRK

#define UART_DM_CR_STO_BRK   0x0060

◆ UART_DM_CR_TEST_FRAME

#define UART_DM_CR_TEST_FRAME   0x00B0

◆ UART_DM_CR_TEST_PARITY

#define UART_DM_CR_TEST_PARITY   0x00A0

◆ UART_DM_CSR_ADDR

#define UART_DM_CSR_ADDR   0x00000008

◆ UART_DM_DMA_EN_RXTX_DM_DIS

#define UART_DM_DMA_EN_RXTX_DM_DIS   0x00

◆ UART_DM_DMEN_ADDR

#define UART_DM_DMEN_ADDR   0x0000003c

◆ UART_DM_DMRX_ADDR

#define UART_DM_DMRX_ADDR   0x00000034

◆ UART_DM_GENERAL_CMD

#define UART_DM_GENERAL_CMD ( a,
v )    UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)
234#define UART_DM_GENERAL_CMD(a, v) \
235 UART_DM_WRITE_REG((a), UART_DM_CR_ADDR, ((v) & 0x7) << 8)

◆ UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE

#define UART_DM_GENERAL_CMD_CR_PROTECTION_DISABLE   0x02

◆ UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE

#define UART_DM_GENERAL_CMD_CR_PROTECTION_ENABLE   0x01

◆ UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT

#define UART_DM_GENERAL_CMD_DISABLE_STALE_EVENT   0x06

◆ UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT

#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT   0x05

◆ UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ

#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ   0x03

◆ UART_DM_GENERAL_CMD_SW_FORCE_STALE

#define UART_DM_GENERAL_CMD_SW_FORCE_STALE   0x04

◆ UART_DM_HCR_ADDR

#define UART_DM_HCR_ADDR   0x00000024

◆ UART_DM_IMR_ADDR

#define UART_DM_IMR_ADDR   0x00000014

◆ UART_DM_IMR_CUR_CTS

#define UART_DM_IMR_CUR_CTS   0x040

◆ UART_DM_IMR_DEFAULT

#define UART_DM_IMR_DEFAULT   0

◆ UART_DM_IMR_DELTA_CTS

#define UART_DM_IMR_DELTA_CTS   0x020

◆ UART_DM_IMR_NONE

#define UART_DM_IMR_NONE   0x000

◆ UART_DM_IMR_RXBREAK

#define UART_DM_IMR_RXBREAK   0x004

◆ UART_DM_IMR_RXHUNT

#define UART_DM_IMR_RXHUNT   0x002

◆ UART_DM_IMR_RXLEV

#define UART_DM_IMR_RXLEV   0x010

◆ UART_DM_IMR_RXSTALE

#define UART_DM_IMR_RXSTALE   0x008

◆ UART_DM_IMR_TX_DONE

#define UART_DM_IMR_TX_DONE   0x200

◆ UART_DM_IMR_TX_ERROR

#define UART_DM_IMR_TX_ERROR   0x100

◆ UART_DM_IMR_TX_READY

#define UART_DM_IMR_TX_READY   0x080

◆ UART_DM_IMR_TXLEV

#define UART_DM_IMR_TXLEV   0x001

◆ UART_DM_IPR_ADDR

#define UART_DM_IPR_ADDR   0x00000018

◆ UART_DM_IPR_DEFAULT

#define UART_DM_IPR_DEFAULT   0x2

◆ UART_DM_IRDA_ADDR

#define UART_DM_IRDA_ADDR   0x00000038

◆ UART_DM_IRDA_DISABLE

#define UART_DM_IRDA_DISABLE   0x00

◆ UART_DM_ISR_ADDR

#define UART_DM_ISR_ADDR   0x00000014

◆ UART_DM_ISR_RXSTALE_BMSK

#define UART_DM_ISR_RXSTALE_BMSK   0x8

◆ UART_DM_ISR_TX_READY_BMSK

#define UART_DM_ISR_TX_READY_BMSK   0x80

◆ UART_DM_MR1_ADDR

#define UART_DM_MR1_ADDR   0x00000000

◆ UART_DM_MR1_CTSC

#define UART_DM_MR1_CTSC   0x40

◆ UART_DM_MR1_DEFAULT

#define UART_DM_MR1_DEFAULT   0

◆ UART_DM_MR1_RFRC

#define UART_DM_MR1_RFRC   0x80

◆ UART_DM_MR2_05SB

#define UART_DM_MR2_05SB   0x00

◆ UART_DM_MR2_15SB

#define UART_DM_MR2_15SB   0x08

◆ UART_DM_MR2_1SB

#define UART_DM_MR2_1SB   0x04

◆ UART_DM_MR2_2SB

#define UART_DM_MR2_2SB   0x0C

◆ UART_DM_MR2_5BPC

#define UART_DM_MR2_5BPC   0x00

◆ UART_DM_MR2_6BPC

#define UART_DM_MR2_6BPC   0x10

◆ UART_DM_MR2_7BPC

#define UART_DM_MR2_7BPC   0x20

◆ UART_DM_MR2_8BPC

#define UART_DM_MR2_8BPC   0x30

◆ UART_DM_MR2_ADDR

#define UART_DM_MR2_ADDR   0x00000004

◆ UART_DM_MR2_DEFAULT

#define UART_DM_MR2_DEFAULT
Value:
(UART_DM_MR2_8BPC | \
UART_DM_MR2_1SB | \
UART_DM_MR2_NOPAR)
UART_DM_MR2_1SB
#define UART_DM_MR2_1SB
Definition msm8x60.c:73
UART_DM_MR2_NOPAR
#define UART_DM_MR2_NOPAR
Definition msm8x60.c:76
UART_DM_MR2_8BPC
#define UART_DM_MR2_8BPC
Definition msm8x60.c:71
163#define UART_DM_MR2_DEFAULT (UART_DM_MR2_8BPC | \
164 UART_DM_MR2_1SB | \
165 UART_DM_MR2_NOPAR)

◆ UART_DM_MR2_EPAR

#define UART_DM_MR2_EPAR   0x02

◆ UART_DM_MR2_ERRMODE

#define UART_DM_MR2_ERRMODE   0x40

◆ UART_DM_MR2_LOOPBACK

#define UART_DM_MR2_LOOPBACK   0x80

◆ UART_DM_MR2_NOPAR

#define UART_DM_MR2_NOPAR   0x00

◆ UART_DM_MR2_OPAR

#define UART_DM_MR2_OPAR   0x01

◆ UART_DM_MR2_SPAR

#define UART_DM_MR2_SPAR   0x03

◆ UART_DM_NO_CHARS_FOR_TX_ADDR

#define UART_DM_NO_CHARS_FOR_TX_ADDR   0x00000040

◆ UART_DM_READ_REG

#define UART_DM_READ_REG ( addr,
offset )    READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))
224#define UART_DM_READ_REG(addr, offset) \
225 READ_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset))

◆ UART_DM_RF_ADDR

#define UART_DM_RF_ADDR   0x00000070

◆ UART_DM_RFWR_ADDR

#define UART_DM_RFWR_ADDR   0x00000020

◆ UART_DM_RX_TOTAL_SNAP_ADDR

#define UART_DM_RX_TOTAL_SNAP_ADDR   0x00000038

◆ UART_DM_RXFS_ADDR

#define UART_DM_RXFS_ADDR   0x00000050

◆ UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK

#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK   0x7f

◆ UART_DM_SIM_CFG_ADDR

#define UART_DM_SIM_CFG_ADDR   0x00000080

◆ UART_DM_SR_ADDR

#define UART_DM_SR_ADDR   0x00000008

◆ UART_DM_SR_ERROR_BMSK

#define UART_DM_SR_ERROR_BMSK
Value:
(UART_DM_SR_UART_OVERRUN_BMSK | \
UART_DM_SR_PAR_FRAME_ERR_BMSK)
UART_DM_SR_PAR_FRAME_ERR_BMSK
#define UART_DM_SR_PAR_FRAME_ERR_BMSK
Definition msm8x60.c:89
UART_DM_SR_UART_OVERRUN_BMSK
#define UART_DM_SR_UART_OVERRUN_BMSK
Definition msm8x60.c:88
92#define UART_DM_SR_ERROR_BMSK (UART_DM_SR_UART_OVERRUN_BMSK | \
93 UART_DM_SR_PAR_FRAME_ERR_BMSK)

◆ UART_DM_SR_HUNT_CHAR_BMSK

#define UART_DM_SR_HUNT_CHAR_BMSK   0x80

◆ UART_DM_SR_PAR_FRAME_ERR_BMSK

#define UART_DM_SR_PAR_FRAME_ERR_BMSK   0x20

◆ UART_DM_SR_RX_BREAK_BMSK

#define UART_DM_SR_RX_BREAK_BMSK   0x40

◆ UART_DM_SR_RXRDY_BMSK

#define UART_DM_SR_RXRDY_BMSK   0x1

◆ UART_DM_SR_TXEMT_BMSK

#define UART_DM_SR_TXEMT_BMSK   0x8

◆ UART_DM_SR_TXRDY_BMSK

#define UART_DM_SR_TXRDY_BMSK   0x4

◆ UART_DM_SR_UART_OVERRUN_BMSK

#define UART_DM_SR_UART_OVERRUN_BMSK   0x10

◆ UART_DM_TF_ADDR

#define UART_DM_TF_ADDR   0x00000070

◆ UART_DM_TFWR_ADDR

#define UART_DM_TFWR_ADDR   0x0000001c

◆ UART_DM_TXFS_ADDR

#define UART_DM_TXFS_ADDR   0x0000004c

◆ UART_DM_WRITE_REG

#define UART_DM_WRITE_REG ( addr,
offset,
val )    WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)
227#define UART_DM_WRITE_REG(addr, offset, val) \
228 WRITE_REGISTER_ULONG((ULONG *)((PUCHAR)addr + offset), val)

◆ UART_RX_BYTES_TO_RECEIVE

#define UART_RX_BYTES_TO_RECEIVE   0x2000

Function Documentation

◆ MSM8x60GetByte()

UART_STATUS MSM8x60GetByte ( _Inout_ PCPPORT Port,
_Out_ PUCHAR Byte )
439{
440 static UINT32 RxWord;
441 static UINT32 Queued = 0;
442 static UINT32 Read = 0;
443 static UINT32 Snap = 0;
444
445 *Byte = 0;
446
447 ULONG limitcount;
448
449 if ((Port == NULL) || (Port->Address == NULL))
450 {
451 return UartNotReady;
452 }
453
454 if (Queued == 0)
455 {
456 PUCHAR Address = Port->Address;
457 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
458 UART_DM_SR_ERROR_BMSK) != 0)
459 {
460 UART_DM_CH_CMD(Address, UART_DM_CH_CMD_RESET_ERROR_STATUS);
461 }
462
463 limitcount = 1;
464 while (limitcount-- != 0)
465 {
466 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
467 UART_DM_SR_RXRDY_BMSK) == 0)
468 {
469 continue;
470 }
471
472 //
473 // Read only if there are more than 4 bytes in the FIFO or RX Stale
474 // occurred
475 //
476
477 if ((UART_DM_READ_REG(Address, UART_DM_RXFS_ADDR) &
478 UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK) == 1)
479 {
480 if ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
481 UART_DM_ISR_RXSTALE_BMSK) == 0)
482 {
483 continue;
484 }
485 }
486
487 RxWord = UART_DM_READ_REG(Address, UART_DM_RF_ADDR);
488 Queued = RX_FIFO_WIDTH;
489 Read += RX_FIFO_WIDTH;
490
491 if (Snap == 0)
492 {
493 if (UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
494 UART_DM_ISR_RXSTALE_BMSK)
495 {
496 Snap = UART_DM_READ_REG(Address,
497 UART_DM_RX_TOTAL_SNAP_ADDR);
498 }
499 }
500
501 if (Snap != 0)
502 {
503 if (Snap <= Read)
504 {
505 if (Snap + RX_FIFO_WIDTH > Read)
506 {
507 Queued = Snap + RX_FIFO_WIDTH - Read;
508 }
509 else
510 {
511 Queued = 0;
512 }
513
514 Read = 0;
515 Snap = 0;
516 UART_DM_CH_CMD(Address, UART_DM_CH_CMD_RESET_STALE_IRQ);
517 UART_DM_WRITE_REG(Address,
518 UART_DM_DMRX_ADDR,
519 UART_RX_BYTES_TO_RECEIVE);
520
521 UART_DM_GENERAL_CMD(Address,
522 UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT);
523 }
524 }
525
526 break;
527 }
528 }
529
530 if (Queued != 0)
531 {
532 *Byte = (int)(RxWord & 0xFF);
533 RxWord = RxWord >> 8;
534 Queued -= 1;
535 return UartSuccess;
536 }
537
538 return UartNoData;
539}
UINT32
unsigned int UINT32
Definition BasicTypes.h:48
ULONG
unsigned long ULONG
Definition BasicTypes.h:37
Address
UINT64 Address
Definition HyperDbgScriptImports.h:67
UART_DM_READ_REG
#define UART_DM_READ_REG(addr, offset)
Definition msm8x60.c:224
UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT
#define UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT
Definition msm8x60.c:219
UART_DM_CH_CMD_RESET_STALE_IRQ
#define UART_DM_CH_CMD_RESET_STALE_IRQ
Definition msm8x60.c:197
UART_DM_RXFS_ADDR
#define UART_DM_RXFS_ADDR
Definition msm8x60.c:46
UART_DM_ISR_RXSTALE_BMSK
#define UART_DM_ISR_RXSTALE_BMSK
Definition msm8x60.c:99
UART_DM_CH_CMD
#define UART_DM_CH_CMD(a, v)
Definition msm8x60.c:230
UART_DM_SR_RXRDY_BMSK
#define UART_DM_SR_RXRDY_BMSK
Definition msm8x60.c:85
UART_DM_CH_CMD_RESET_ERROR_STATUS
#define UART_DM_CH_CMD_RESET_ERROR_STATUS
Definition msm8x60.c:192
UART_DM_SR_ERROR_BMSK
#define UART_DM_SR_ERROR_BMSK
Definition msm8x60.c:92
UART_DM_DMRX_ADDR
#define UART_DM_DMRX_ADDR
Definition msm8x60.c:39
UART_DM_ISR_ADDR
#define UART_DM_ISR_ADDR
Definition msm8x60.c:33
UART_RX_BYTES_TO_RECEIVE
#define UART_RX_BYTES_TO_RECEIVE
Definition msm8x60.c:21
RX_FIFO_WIDTH
#define RX_FIFO_WIDTH
Definition msm8x60.c:22
UART_DM_RF_ADDR
#define UART_DM_RF_ADDR
Definition msm8x60.c:48
UART_DM_SR_ADDR
#define UART_DM_SR_ADDR
Definition msm8x60.c:30
UART_DM_RX_TOTAL_SNAP_ADDR
#define UART_DM_RX_TOTAL_SNAP_ADDR
Definition msm8x60.c:41
UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK
#define UART_DM_RXFS_RX_FIFO_STATE_LSB_BMSK
Definition msm8x60.c:106
UART_DM_GENERAL_CMD
#define UART_DM_GENERAL_CMD(a, v)
Definition msm8x60.c:234
util.Read
Read(Tokens)
Definition util.py:6

◆ MSM8x60InitializePort()

BOOLEAN MSM8x60InitializePort ( _In_opt_ _Null_terminated_ PCHAR LoadOptions,
_Inout_ PCPPORT Port,
BOOLEAN MemoryMapped,
UCHAR AccessSize,
UCHAR BitWidth )
281{
282 UNREFERENCED_PARAMETER(LoadOptions);
283 UNREFERENCED_PARAMETER(AccessSize);
284
285 if (MemoryMapped == FALSE)
286 {
287 return FALSE;
288 }
289
290 if (BitWidth != 32)
291 {
292 return FALSE;
293 }
294
295 Port->Flags = 0;
296
297 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_DIS_RX);
298 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_DIS_TX);
299 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_ERR);
300 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_RX);
301 UART_DM_WRITE_REG(Port->Address, UART_DM_CR_ADDR, UART_DM_CR_RESET_TX);
302 UART_DM_WRITE_REG(Port->Address, UART_DM_MR1_ADDR, UART_DM_MR1_DEFAULT);
303 UART_DM_WRITE_REG(Port->Address, UART_DM_MR2_ADDR, UART_DM_MR2_DEFAULT);
304
305 MSM8x60SetBaud(Port, Port->BaudRate);
306
307 UART_DM_WRITE_REG(Port->Address, UART_DM_IMR_ADDR, UART_DM_IMR_DEFAULT);
308 UART_DM_WRITE_REG(Port->Address, UART_DM_IPR_ADDR, UART_DM_IPR_DEFAULT);
309 UART_DM_WRITE_REG(Port->Address, UART_DM_BADR_ADDR, UART_DM_BADR_DEFAULT);
310 UART_DM_WRITE_REG(Port->Address, UART_DM_DMEN_ADDR, 0);
311 UART_DM_WRITE_REG(Port->Address, UART_DM_DMRX_ADDR, UART_RX_BYTES_TO_RECEIVE);
312 UART_DM_CH_CMD(Port->Address, UART_DM_CH_CMD_RESET_STALE_IRQ);
313 UART_DM_GENERAL_CMD(Port->Address, UART_DM_GENERAL_CMD_ENABLE_STALE_EVENT);
314 UART_DM_WRITE_REG(Port->Address,
315 UART_DM_CR_ADDR,
316 (UART_DM_CR_ENA_RX | UART_DM_CR_ENA_TX));
317
318 return TRUE;
319}
TRUE
#define TRUE
Definition BasicTypes.h:55
FALSE
#define FALSE
Definition BasicTypes.h:54
UART_DM_CR_RESET_ERR
#define UART_DM_CR_RESET_ERR
Definition msm8x60.c:125
UART_DM_IPR_DEFAULT
#define UART_DM_IPR_DEFAULT
Definition msm8x60.c:172
UART_DM_MR2_DEFAULT
#define UART_DM_MR2_DEFAULT
Definition msm8x60.c:163
UART_DM_MR2_ADDR
#define UART_DM_MR2_ADDR
Definition msm8x60.c:29
UART_DM_IMR_ADDR
#define UART_DM_IMR_ADDR
Definition msm8x60.c:34
UART_DM_CR_DIS_RX
#define UART_DM_CR_DIS_RX
Definition msm8x60.c:119
UART_DM_CR_RESET_RX
#define UART_DM_CR_RESET_RX
Definition msm8x60.c:123
UART_DM_CR_ENA_RX
#define UART_DM_CR_ENA_RX
Definition msm8x60.c:118
UART_DM_CR_DIS_TX
#define UART_DM_CR_DIS_TX
Definition msm8x60.c:121
UART_DM_DMEN_ADDR
#define UART_DM_DMEN_ADDR
Definition msm8x60.c:42
UART_DM_BADR_DEFAULT
#define UART_DM_BADR_DEFAULT
Definition msm8x60.c:178
UART_DM_CR_ENA_TX
#define UART_DM_CR_ENA_TX
Definition msm8x60.c:120
UART_DM_MR1_ADDR
#define UART_DM_MR1_ADDR
Definition msm8x60.c:28
UART_DM_IMR_DEFAULT
#define UART_DM_IMR_DEFAULT
Definition msm8x60.c:166
MSM8x60SetBaud
BOOLEAN MSM8x60SetBaud(_Inout_ PCPPORT Port, ULONG Rate)
Definition msm8x60.c:322
UART_DM_BADR_ADDR
#define UART_DM_BADR_ADDR
Definition msm8x60.c:44
UART_DM_MR1_DEFAULT
#define UART_DM_MR1_DEFAULT
Definition msm8x60.c:162
UART_DM_CR_RESET_TX
#define UART_DM_CR_RESET_TX
Definition msm8x60.c:124
UART_DM_IPR_ADDR
#define UART_DM_IPR_ADDR
Definition msm8x60.c:35

◆ MSM8x60PutByte()

UART_STATUS MSM8x60PutByte ( _Inout_ PCPPORT Port,
UCHAR Byte,
BOOLEAN BusyWait )
568{
569 PUCHAR Address;
570
571 if ((Port == NULL) || (Port->Address == NULL))
572 {
573 return UartNotReady;
574 }
575
576 Address = Port->Address;
577
578 if ((UART_DM_READ_REG(Address, UART_DM_SR_ADDR) &
579 UART_DM_SR_TXEMT_BMSK) == 0)
580 {
581 if (BusyWait != FALSE)
582 {
583 while ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
584 UART_DM_ISR_TX_READY_BMSK) == 0)
585 ;
586 }
587 else if ((UART_DM_READ_REG(Address, UART_DM_ISR_ADDR) &
588 UART_DM_ISR_TX_READY_BMSK) == 0)
589 {
590 return UartNotReady;
591 }
592 }
593
594 UART_DM_WRITE_REG(Address, UART_DM_NO_CHARS_FOR_TX_ADDR, 1);
595 UART_DM_GENERAL_CMD(Address, UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ);
596 UART_DM_WRITE_REG(Address, UART_DM_TF_ADDR, (UINT32)Byte);
597 return UartSuccess;
598}
UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ
#define UART_DM_GENERAL_CMD_RESET_TX_READY_IRQ
Definition msm8x60.c:217
UART_DM_NO_CHARS_FOR_TX_ADDR
#define UART_DM_NO_CHARS_FOR_TX_ADDR
Definition msm8x60.c:43
UART_DM_SR_TXEMT_BMSK
#define UART_DM_SR_TXEMT_BMSK
Definition msm8x60.c:87
UART_DM_ISR_TX_READY_BMSK
#define UART_DM_ISR_TX_READY_BMSK
Definition msm8x60.c:100
UART_DM_TF_ADDR
#define UART_DM_TF_ADDR
Definition msm8x60.c:47

◆ MSM8x60RxReady()

BOOLEAN MSM8x60RxReady ( _Inout_ PCPPORT Port)
620{
621 UINT32 Sr;
622
623 if ((Port == NULL) || (Port->Address == NULL))
624 {
625 return FALSE;
626 }
627
628 Sr = UART_DM_READ_REG(Port->Address, UART_DM_SR_ADDR);
629 if (CHECK_FLAG(Sr, UART_DM_SR_RXRDY_BMSK))
630 {
631 return TRUE;
632 }
633
634 return FALSE;
635}
CHECK_FLAG
#define CHECK_FLAG(_x, _f)
Definition uartp.h:27

◆ MSM8x60SetBaud()

BOOLEAN MSM8x60SetBaud ( _Inout_ PCPPORT Port,
ULONG Rate )
344{
345 UINT32 DivisorLatch;
346
347 if ((Port == NULL) || (Port->Address == NULL))
348 {
349 return FALSE;
350 }
351
352 //
353 // Clock rate is 1843200.
354 //
355
356 switch (Rate)
357 {
358 case 75:
359 DivisorLatch = 0x00;
360 break;
361 case 150:
362 DivisorLatch = 0x11;
363 break;
364 case 300:
365 DivisorLatch = 0x22;
366 break;
367 case 600:
368 DivisorLatch = 0x33;
369 break;
370 case 1200:
371 DivisorLatch = 0x44;
372 break;
373 case 2400:
374 DivisorLatch = 0x55;
375 break;
376 case 3600:
377 DivisorLatch = 0x66;
378 break;
379 case 4800:
380 DivisorLatch = 0x77;
381 break;
382 case 7200:
383 DivisorLatch = 0x88;
384 break;
385 case 9600:
386 DivisorLatch = 0x99;
387 break;
388 case 14400:
389 DivisorLatch = 0xAA;
390 break;
391 case 19200:
392 DivisorLatch = 0xBB;
393 break;
394 case 28800:
395 DivisorLatch = 0xCC;
396 break;
397 case 38400:
398 DivisorLatch = 0xDD;
399 break;
400 case 57600:
401 DivisorLatch = 0xEE;
402 break;
403 case 115200:
404 DivisorLatch = 0xFF;
405 break;
406 default:
407 DivisorLatch = 0xFF;
408 break;
409 }
410
411 UART_DM_WRITE_REG(Port->Address, UART_DM_CSR_ADDR, DivisorLatch);
412 Port->BaudRate = Rate;
413 return TRUE;
414}
UART_DM_CSR_ADDR
#define UART_DM_CSR_ADDR
Definition msm8x60.c:31

Variable Documentation

◆ MSM8x60HardwareDriver

UART_HARDWARE_DRIVER MSM8x60HardwareDriver
Initial value:
= {
MSM8x60InitializePort,
MSM8x60SetBaud,
MSM8x60GetByte,
MSM8x60PutByte,
MSM8x60RxReady}
MSM8x60PutByte
UART_STATUS MSM8x60PutByte(_Inout_ PCPPORT Port, UCHAR Byte, BOOLEAN BusyWait)
Definition msm8x60.c:542
MSM8x60GetByte
UART_STATUS MSM8x60GetByte(_Inout_ PCPPORT Port, _Out_ PUCHAR Byte)
Definition msm8x60.c:417
MSM8x60InitializePort
BOOLEAN MSM8x60InitializePort(_In_opt_ _Null_terminated_ PCHAR LoadOptions, _Inout_ PCPPORT Port, BOOLEAN MemoryMapped, UCHAR AccessSize, UCHAR BitWidth)
Definition msm8x60.c:247
MSM8x60RxReady
BOOLEAN MSM8x60RxReady(_Inout_ PCPPORT Port)
Definition msm8x60.c:601
639 {
640 MSM8x60InitializePort,
641 MSM8x60SetBaud,
642 MSM8x60GetByte,
643 MSM8x60PutByte,
644 MSM8x60RxReady};